深槽技術於CMOS共平面波導與晶片隔絕度之應用

Deep Trench Technology for CMOS CPW and On-Chip Isolation

呂學士(Shey-Shi Lu) ； 汪濤(Tao Wang)

《科儀新知》 166期 (2008/10) Pp. 42-47

https://doi.org/10.29662/IT.200810.0005

摘要

本研究將微機電深槽技術應用於CMOS射頻積體電路之共平面波導，晶片製作後，將該共平面波導底下之損耗基板，以微機電製程之電感型耦合電漿蝕刻技術移除，並於量測散射參數（S參數）後，由量測數據萃取其傳輸線等效電路。實驗結果顯示，在20 GHz時移除基板損耗後，此傳輸線之效能提升，其訊號衰減率由原本0.5 dB/mm降至0.05 dB/mm；寄生電容(capacitance)降低為原本的56%，寄生之基板電納(conductance)則由原本的1.6 mS/mm降至近乎0 mS/mm的程度。本文除了驗證此深槽技術能消除共平面波的基板損耗，並進一步討論該技術對於晶片隔絕度(on-chip isolation)之改善，實驗結果顯示，晶片隔絕度於2 GHz時可增加近32 dB。上述種種優點說明本技術不僅改善共平面波導的性能，也可使電路透過基板的干擾降低，對未來CMOS微波領域或系統單晶化(system-on-a-chip)的應用具有相當潛力。

並列摘要

A coplanar waveguide (CPW) was implemented in 0.13 mm CMOS technology and then post-processed by CMOS compatible inductively-coupled plasma (ICP) etching, which removes the silicon underneath the coplanar strips. Transmission line parameters such as characteristic impedance Z0, attenuation constant, substrate capacitance/conductance C/G, series inductance/resistance L/R, as a function of frequency were extracted. It is found that α, C and G are greatly improved after silicon removal. At 20 GHz, α is decreased from 0.5 dB/mm to 0.05 dB/mm, G is reduced from 1.6 mS/mm to~0 mS/mm and C is lowered by 56%. The experiment shows that deep trench technology is capable to promote the performance of coplanar waveguide profoundly. Besides the CPW, the technique was further used for on-chip isolation purpose, aimed to solve the problem of substrate leakage. The result shows an extra 32 dB isolation at 2 GHz was contributed by this technique. From these experiments, it is evidenced that deep trench technology should be promising in CMOS MMIC and SOC applications.