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CMP佈局平坦化的階層式密度分析方法

Hieratical Layout Density Analysis for CMP Planarization

摘要


化學機械研磨(chemical-mechanical polishing, CMP)技術是目前後端製程所必須的程序,爲提高CMP 程序後整體的平坦度,需在晶片佈局產生後加入虛擬金屬(dummy fill)填充。在安插虛擬金屬填充前,必須先對晶片佈局做密度分析,讓虛擬金屬有效的安插運用以防止虛擬金屬被安插在錯誤的地方。首先,本文提出階層式的方法來進行密度分析,作爲計算各個方格(tile)需安插的虛擬金屬填充數量的依據。本文所提出階層式的密度分析方法,兼具執行效率與結果精確度的優點。以ISCAS89 測試電路組的實驗數據顯示,本文提出的密度分析方法,在效率與精確度都明顯優於固定分割密度分析方法(fixed-dissection density analysis)。

並列摘要


Chemical-Mechanical Polishing (CMP) technology is an important procedure in the fabrication of chips to enhance the overall smoothness needed for increasing the yield. Insertion of dummy fill is an important issue for CMP planarization in the back-end synthesis flow of IC (integrated circuit) design. Layout density analysis is the basis for calculating the amount of dummy fill needed for CMP planarization. In this article, we propose a hierarchical approach to layout density analysis. The proposed method has the advantages of both efficiency and accuracy. The experimental results with the ISCAS89 benchmark show that the proposed method outperforms the Fixed-Dissection Density Analysis approach.

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