應用於CMOS奈米製程之鎖相迴路抖動改善技術

Jitter-Improved Techniques for PLLs in Nano Scale CMOS Process

洪兆慶(Chao-Ching Hung)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.01347

摘要

持續演進且縮小尺寸的CMOS製程，使得操作於幾十GHz的高速電路得以用CMOS實現，並與先進通訊系統中龐大的數位電路相整合。不過製程中的漏電流也越來越明顯，會造成鎖相迴路額外的抖動。另外，數位化的鎖相迴路可以減少製程轉換所需的設計時間、對雜訊有較大的容忍度、也能利用數位的方式提供更多校正的功能，因此，如何將全數位鎖相迴路應用在射頻系統，也是研究的重點之一。
首先，我們提出一個應用在鎖相迴路中的漏流校正。借由我們所提出的電路與設計方法，漏電流造成的抖動與晶片的面積皆大幅減少。以65nm CMOS製作，此晶片抖動RMS大小從無法鎖定到3.1ps；以1.2V為供應電壓；功率消耗為10mW；所佔面積為0.14mm2。接下來，我們進一步最佳化漏流校正的方法，使得晶片面積更小、漏電流的功耗更小、電源的雜訊偶合量更小。以65nm CMOS製作，此晶片抖動RMS大小從無法鎖定到5.13ps；以1.2V為供應電壓；功率消耗為3.6mW；所佔面積為0.065mm2。
正如人們所熟知的，分數型頻率合成器(fractional-N frequency synthesizer)是現在射頻系統中提供時脈的重要電路。利用三角積分調變器(delta sigma modulator)合成出更小的頻率間隔，然而三角積分調變器本身的量化雜訊以及相位頻率偵測器(phase frequency detector)/充電泵(charge pump)的非線性都會使頻率合成器的雜訊表現變差。為了同時解決這兩個問題，我們使用了雜訊濾波器(noise filter)的概念，同時抑制這兩種雜訊。此電路以90nm數位CMOS製程製造，以1V為供應電壓，整個頻率合成器消耗30mW，積分相位雜訊從2.045度改善至1.343度。
最後，我們提出了一個40GHz的全數位鎖相迴路。為了改善抖動，提出一個新型的變電容(varactor)架構，使得數位控制振盪器(digital controlled oscillator)達到更精細的頻率解析度。就作者所知，這個作品目前是最高頻的全數位鎖相迴路。另外，砰砰 (bang-bang) 相位偵測器 (phase detector)最為人詬病的就是較長的鎖定時間，為了改進這個缺點，我們修改了砰砰相位偵測器的操作方式，使得鎖定時間可以大幅的縮減。此電路以90nm數位CMOS製程製造，以1.2V為供應電壓，整個全數位鎖相迴路消耗46mW，面積為0.3 mm2，鎖定時間為15us，RMS抖動大小為300.87fs。

關鍵字

CMOS奈米製程 ； 鎖相迴路 ； 抖動改善技術

並列摘要

The continuous scaling of CMOS technology has opened the opportunity to integrate high-speed circuits operating at tens of gigahertz together with the large digital portion of modern communication systems. However, the order of the leakage current increases dramatically, which causes additional jitters in phase-locked loop. In addition, the digitalized phase-locked loop can reduce the design time from one process to another, have more tolerances to the noise, provide a variety of calibrations in digital way. Therefore, it is worth to investigate how to design an all-digital phase-locked loop in RF systems.
First of all, a leakage calibration for phase-locked loops is presented. By using the proposed circuit and design methodology, the jitter due to the leakage current and chip area are both reduced. Fabricated in a 65nm CMOS process, the IC prototype achieves a RMS jitter of 3.1ps comparing with unlocked state initially. It consumes 10 mW from a 1.2 V supply and occupies an area of only 0.14 mm2. Next, an optimal methodology is proposed to achieve smaller chip area, less power consumption due to leakage current, and less noise coupling from power supply. Fabricated in a 65nm CMOS process, the IC prototype achieves a RMS jitter of 5.13ps comparing with unlocked state initially. It consumes 3.6 mW from a 1.2 V supply and occupies an area of only 0.065 mm2.
As everyone knows, fractional-N frequency synthesizers are the key circuits to provide the clocks in RF systems. Finer frequency hopping is achieved by using the delta sigma modulation. However, the quantization noise of the delta sigma modulator and the nonlinearity of the phase frequency detector and charge pump make the phase noise of the frequency synthesizer more worse. In order to solve these two problems, an idea of noise filtering is proposed to reduce these two impacts. Fabricated in 90nm digital CMOS technology, the overall frequency synthesizer consumes 30mW from a 1V supply. The integrated phase noise is improved from 2.045。 to 1.343。.
Finally, a 40GHz all digital phase-locked loop is proposed. In order to reduce the jitter, a novel varactor topology is proposed. Therefore, finer frequency resolution of digital controlled oscillator is achieved. To authors’ knowledge, the operation frequency of this work is the highest in the world. In addition, the known drawback of the bang-bang phase detector is longer lock time. In order to reduce the lock time substantially, a modified bang-bang operation is proposed. Fabricated in 90nm CMOS technology, the all digital phase locked loop consumes 46mW from a 1.2V supply. The chip area is 0.3 mm2. The lock time is 15us. The RMS jitter is 300.87fs.

並列關鍵字

jitter-improved techniques ； PLL ； nano scale CMOS process

參考文獻

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