適用於三維積體電路的溫度感知測試排程與可測試設計之最佳化

Thermal-aware Test Scheduling and TAM Optimization for 3D IC

許智堯(Chih-Yao Hsu)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.02250

摘要

三維積體電路相較於傳統的二維積體電路有許多的優點，例如較短的連線，更好的效能，高堆疊密度等等。然而，雖然三維積體電路有如此多的好處，但是還是有許多問題有待解決。其中，在所有電子設計自動化領域中，三維積體電路的測試方法被視為最困難的挑戰。而且，三維積體電路所造成的高功率密度會造成晶片溫度上升，而在高溫環境之下，會造成良率下降的問題。所以三維積體電路的熱管理機制是非常重要的。
此篇論文提出一個針對三維積體電路之熱感知測試排程與可測試設計之最佳化，此測試排程之最高溫度小於所給定之最高溫度限制。在我們的最佳化過程中，我們採用了一個廣為人知的最佳化演算法，模擬退火法(simulated annealing)。我們所提出的技術支援兩種最佳化模式，可以依據不同的三維積體電路選擇不同之最佳化模式。在此論文中，我們提出了一個簡化的熱電阻模型來預測不同時間下測試排程的最高溫度。在我們的實驗結果中，我們所提出技術所產生之測試排成，在整體測試時間來說，比沒有加入溫度限制的方法增加約20%。但是所產生之測試排成，其最高溫度都小於所給定之最高溫度。經由我們提出的熱電阻模型與一個學術上廣泛使用的熱模擬器的模擬溫度誤差都小於3%的差距。以外，我們所提出的熱電組模型可以節省相當多熱模擬時間相較於此熱模擬器。

關鍵字

測試排程 ； 可測試設計 ； 三維積體電路

並列摘要

Three-dimensional integrated circuits (3D ICs) have many advantages over traditional integrated circuits such as shorter global interconnect, higher performance, higher packing density, and so on. Although 3D ICs have such advantages, there are many difficulties to be overcome. Testing for 3D ICs is regarded as the most difficult challenge in the EDA area. Besides, the high power density in 3D ICs causes the temperature rising. Thus, high temperature may cause test yield loss. As a result, temperature management technique is critical for 3D ICs.
A thermal-aware test scheduling and TAM optimization technique for 3D ICs is proposed to compute a test schedule, in which the maximum temperature is under temperature limit. In our optimization process, we adopt a well-known optimization algorithm, simulated annealing. Two optimization modes are supported by the proposed technique for the designer to choose based on different 3D IC configuration. A simplified thermal resistance model is proposed in our optimization process to estimate the maximum temperature in the test schedule. Our experimental results show that the test length of our proposed technique is only about 20% longer in average than the test scheduling method without temperature limit. However, the maximum temperature in the test schedule of our proposed technique is under the temperature limit. The temperature error rate between our proposed thermo-resistance model and an academic thermal simulator is below 3%. Besides, our proposed thermal model can save great simulation time compared with a popular thermal simulator.

並列關鍵字

Test Scheduling ； TAM ； 3D IC

參考文獻

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