可攜式全數位鎖相迴路電路設計與實現

Design and Implementation of Portable All-Digital PLLs

吳嘉村(Chia-Tsun Wu)

指導教授 ： 吳安宇

國立臺灣大學/電機資訊學院/電機工程學研究所/博士(2010年)

https://doi.org/10.6342/NTU.2010.02868

摘要

自從1932年第一個鎖相迴路(phase locked loop，PLL)電路被設計出來以來，到目前為止針對各種不同的應用已經發展出各式各樣的鎖相迴路電路。最近幾年針對系統晶片(SoC)的應用，有一種被稱為全數式鎖相迴路(all-digital phase-locked loop，ADPLL)的新型鎖相迴路被大量的探討，主要原因是，隨著積體電路(integrated circuit, IC)功能性高度的整合之下，常常需要在一顆晶片(chip)之中整合大量而且不同的電路，通常這些電路都需要一個可靠的時脈(clock)做為電子電路工作的參考依據。全數位式鎖相迴路電路因為不使用任何的電阻電容電感(RLC)做為電路的零件(component)使得這種基於數位設計方法的鎖相迴路不但很容易被整合入系統晶片，而且還同時具有體積小的優點。
然而全數位式鎖相迴路對於數位控制振盪器(digitally-controlled oscillator，DCO)的控制只能在有限的解析度下進行操作，通常為幾10個微微秒(picosecond)至100多個微微秒，對於非線性微分(differential non-linearity，DNL)的表現他非常的不盡理想。為了保有全數式鎖相迴路電路之優點並且同時改進其缺點，本論文提出了數個基於數位信號處理的演算法來大幅改進這些缺點，在聯華電子 0.18微米之互補式金屬氧化物半導體製程(UMC 0.18µm CMOS process)驗証下，能達到0.03毫米平方(mm2) 的大小。
本論文從第三章開始針對全數位式鎖相迴路之各設計單元提出一個可以同時改進其效能，並同時維持小面積的創新或改進電路。這些電路有些是基於現有的研究成果加以改進，有些則是透過數位信號處理演算法推導後提出的新創想法。在數位控制振盪器方面本文提出一個系統的建構方式來產生振盪器電路，這樣的方法即便在不同的製程下也能很快的建構出符合規格的振器電路。這幾年，高速的數位電路均採用雙倍資料流(double data rate，DDR)的設計技巧，針對這類需要50%工作週期(duty cycle)的時脈需求，本文也提出了一個全數位式脈宽控制迴路設計以符合高速電路的需求。另外，一般而言全數式鎖相迴路的迴路頻宽(loop bandwidth)都不高，約不到輸入參考信號的千分之一，使得全數位式鎖相迴路的迴路嚮應不好，在論文中會提出一個可適性之迴路濾波器使得全數式鎖相迴路的頻率嚮應可以大幅提升至數百倍的輸入時脈，由於迴路頻宽會基於迴路狀況自動的調整至合適的頻宽，因此可以大幅的提升迴路嚮應的效能，更可貴的是這個被優化過的演算法在硬體實現的結果指出硬體需求還比原來方法實現更低。除了以上三點的突破外，在全數位式鎖相迴路中最被引以為傲的鎖定時間(lock-in time)我們也提出一個全新的演算法，相較於目前最好的研究論文比較之下提升至3.5倍效能。
基於前述所提出的四點創新，本論文針對了全數位式鎖相迴路的每一主要電路都做了相當的優化，所有的設計都是基於硬體描述語言(hardware description language，HDL)設出來，這樣的設計不僅非常適合於系統晶片內的整合，同時也非常容易在不用的製程或設計規格之間轉換。總結本論文所提出上述四種創新的全數位式鎖相迴路設計方式，皆可同時改進全數位式鎖相迴路電路設計，並針對如何快速設計可攜式全數式鎖相迴路有深入的探討，搭配standard cell設計流程，可以在最短的時程內設計出目標之迴相迴路電路。本論所提出各種設計電路都經過晶片設計來驗證所提出這四種全數位式鎖相迴路的設計方法。

關鍵字

鎖相迴路 ； 全數位鎖相迴路 ； 快速鎖定

並列摘要

Different kinds of phase-locked loops (PLL) have been developed for various applications since the design of the first PLL in 1932. In recent years, the all-digital phase-locked loop (ADPLL) has been broadly studied for System-on-Chip (SoC) applications, because many designs need to be integrated into one chip in the SoC environment. In a majority of cases, these designs need a reliable clock source to work. As there is no RLC component involved in the ADPLL design, the ADPLL offers the dual advantage of being easy to integrate and entailing very low hardware overhead. From this point of view, the ADPLL offers the advantages of not only reducing both the production and design cost, but can also be produced for market in a very short span of time.
In Chapter 3~5, the dissertation presents improved circuits for each module of the ADPLL. Some of these modules are an improvement on recent published research while some have been newly developed using the DSP algorithm. All these modules maintain low hardware overhead along with good performance. This thesis also presents a systematic methodology to construct the DCO circuit. The new design methodology achieves a very low design cycle time for various processes and design specifications. In recent years, double data rate (DDR) circuits have become the major design components of high-speed circuits. This thesis also describes the operation of an all-digital pulse width control loop (ADPWCL), to produce an output equal to 50% of the duty cycle of the ADPLL for such high-speed circuits. In addition, the loop bandwidth of the ADPLL is usually lower and typically less than 1/1000 of the reference clock to yield a low loop response. In Chapter 3, this thesis presents an adaptive loop filter to adjust the loop bandwidth from a 100x to a value of <1/1000 reference clock. This is because the adaptive loop filter has the ability to adjust its loop bandwidth dynamically using its phase error. The optimized algorithm and hardware demonstrate a more compact hardware requirement as compared to current research and enable a high tracking performance with respect to the input reference clock. Lastly, this thesis also presents a new frequency estimation algorithm, which demonstrates a 350% improvement on the lock-in time as compared to the current state of the art.
Using the new approaches, we have developed many circuits based on the hardware description language (HDL). The developed ADPLL designs are not only easy to integrate into the SoC chip but also can also easily be applied to various CMOS processes.
In summary, the new approaches presented in this dissertation improve the overall design and performance of the ADPLL. All the proposed designs have been verified using a highly portable chip-level design.

並列關鍵字

PLL ； ADPLL ； fast locked

參考文獻

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