Dynamically Reconfigurable Hardware Library based of FPGA

Dynamically Reconfigurable Hardware Library based of FPGA

何建緯(Chien-Wei Ho)

指導教授 ： 顧孟愷

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.02929

摘要

無資料

關鍵字

現場可重定址陣列 ； 系統晶片 ； 矽智財

並列摘要

Nowadays when we want to do a design, we need to software-hardware partition first. It is because that we want to put some heavy loading parts of the design into hardware. That would improve the performance of the whole design. Generally if we can put as many functions into hardware as we can, we will get much performance improvement. So, besides the software-hardware partitioning consideration, we need to have a rapidly method to let the Compute Intensive Part (CIP) run in hardware. We propose a Dynamically Reconfigurable Hardware Library (DRHL) method. When we put the CIP into DRHL, we can change to use software Intellectual Property (IP) or hardware IP smoothly. So, we can easily test if our software IP and hardware IP have the same functionality. We also can enhance computation power in System-On-Chip (SOC) with FPGA blocks. Our method provides to reach a better trade-off among flexibility performance and power.

並列關鍵字

FPGA ； SOC ； IP

參考文獻

REFERENCES (WORKS CITED, SELECTED BIBLIOGRAPHY)

[3] S. Hauck, “The roles of FPGAs in reprogrammable systems,” Proceedings of the IEEE, vol. 86, pp. 615-638, April 1998.

[4] P Brunet, C Tanougast, and Y Berviller, “Hardware Partitioning Software for Dynamically Reconfigurable SoC Design,” Proceedings of the 3rd IEEE International Workshop, pp. 106-111, July 2003.

[5] J. Harkin, T. M. McGinnity, and L. P. Maguire, “Partitioning methodology for dynamically reconfigurable embedded systems,” IEEE Proceedings - Computers and Digital Techniques, vol.147, pp. 391-396, November 2000.

[6] Sitanshu Jain, “Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library,” Proceedings of IEEE international conference on VLSI design, pp. 400-405, Jan. 1998.