數位邏輯分析儀設計

隨著數位系統的日益進步和複雜，預料工程師將需要在邏輯分析儀畫面上檢視大量的資料來有效地解讀日益膨脹的訊號與程式碼內容。再者，工程師已不再侷限於定點工作，攜帶著邏輯分析儀去客戶端除錯使得攜帶型的邏輯分析儀的性能及需求量也大增。現今儀器平台型的邏輯分析儀擁有良好的性能，如可量測高頻的數位訊號、高取樣頻率、高運算速度、高速度的觸發擷取功能、容量大的記憶體深度等等，但價格昂貴且缺點為太重而不易攜帶。口袋型(或稱為PC-Based)的邏輯分析儀除了容易攜帶的優點外，價格也相較便宜許多，其性能因受限於內部沒有高效能的微處理器而使得可量測的數位訊號、取樣頻率、運算速度、觸發擷取功能、記憶體深度等等已不足以量測現今大多數的數位系統。本論文是以設計並實作出高性能、易攜帶及低單價的邏輯分析儀為研究重點，並且以CPLD為設計元件，省了開IC或ASIC的製作費用及避免了開IC或ASIC失敗的風險。而在技術上以突破CPLD本身元件工作頻率規格2倍以上的鎖相倍頻的做法來達到高取樣頻率。又以CPLD來設計觸發擷取功能，並設計出新的方法能在不需使用高效能的微處理器就可達到高速度的觸發擷取功能，相較於以往需使用工作頻率高於取樣頻率的微處理器來做觸發擷取功能的方式，本論文則是以低於取樣頻率5倍以上的工作頻率達到觸發擷取功能。就IC設計製造及成本的觀點，上述兩點均是以低工作頻率來達到高的性能，而高工作頻率的IC價格可能是低工作頻率IC價格的數倍以上。另外，本論文是以SDRAM來做為記憶體深度，以SDRAM的發展來看，其記憶容量及存取速度是不斷在進步的，故以SDRAM來做記憶深度的設計考量是足以對應未來日益膨脹的訊號量與程式碼容量的需求。

關鍵字

邏輯分析儀；取樣；觸發擷取；鎖相倍頻

並列摘要

As the development of digital system progresses day by day, engineers must rely on logic analyzer to analyze and understand a lot of signals and program codes. Moreover, engineers do not always work in the company. It is necessary to take the logic analyzer to customers for debug service such PC-based logic analyzer with good performance is required. Instrument type of logic analyzer has good performance with high frequency bandwidth, high sample rate, high operation speed, high speed of trigger latch function, width memory depth…etc. However, it is so expensive and too heavy that it is difficult to carry. The price of Pocket type (or called PC-based type) of logic analyzer is much cheaper and is easy to carry. However, the performance of Pocket type of logic analyzer is limited. Since there is no microprocessor inside Pocket type of logic analyzer such that frequency bandwidth, sample rate, operation speed, trigger latch function, memory depth…etc are not to suitable for measurements for most high speed digital system nowadays. In this paper, the design and implementation of a logic analyzer with high performance, easy to carry and low cost are focused. CPLD is used for considerations of cost and design risk. Technically, we use different DLL and data transforms methods to perform high sampling rate and high speed triggering latch function without high operation speed microprocessor. Our design is based on CPLD so that the cost of components is less expensive than that of with high operation speed microprocessor method. In addition, we use SDRAM for storing device for memory depth. According to development of SDRAM, the capacity and access speed of SDRAM are progressing constantly. So using SDRAM as the design of memory depth will meet the requirement of digital system in the future.

並列關鍵字

Logic analyzer ； Sample rate ； Trigger latch function ； DLL

參考文獻

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Microsoft Press,1996

國際替代計量

數位邏輯分析儀設計

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