考慮時序之時脈閘控電路最佳化

Optimization of Clock Gating Circuits with Timing Considerations

莊舜翔(Shun-Hsiang Chuang)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.03413

摘要

在現今的積體電路設計流程中，功率消耗已成為一大瓶頸。因此，一種被稱為時脈閘控的高效益省電技術，經常被拿來使用以降低晶片所消耗的功率。一般來說，時脈閘控的基本架構可大略分成為三大部分：(1)時脈閘控訊號控制系統、(2)暫存器狀態控制系統、以及 (3)時脈閘控電路。近幾年來，研究員大多致力於關於時脈閘控訊號控制系統、以及暫存器狀態控制系統的簡化研究。相較之下，時脈閘控電路的最佳化反而較少被提及。據我們所知，本論文提出首份有關在時序限制的考量下，時脈閘控電路之最佳化的研究。我們提出了一種V型的最佳化流程，其中包括了由總體至個別區塊的分割、以及由個別區塊至總體的合併。實驗結果顯示了本論文所提出的最佳化流程所達到的顯著效果。相較於九十九學年度大學校院積體電路電腦輔助設計軟體製作競賽中前三名之隊伍，平均來說，我們能達到多達14.6%的更佳效果。同時，當在時序限制較難達到的情況下，我們還能有效地得到最佳化結果。反觀競賽前三名之隊伍，他們皆無法在時序限制較嚴格的情況下，產生任何最佳化的結果。

關鍵字

時脈閘控 ； 功率消耗 ； 時序考量 ； 低功耗技術

並列摘要

Power consumption is an essential concern in modern circuit designs. Clock gating, an efficient technique for power reduction, has been widely used. The basic structure of a circuit using clock gating could generally be classified into three major parts: the clock-gating function, the next state function, and the clock-gating circuits. In recent years, researchers have mainly focused on simplifications of the next-state function and the clock-gating function. In contrast, the optimization of the clock-gating circuit has seldom been addressed. To the best of our knowledge, we introduce the first work in the literature that addresses on the optimization of the clock-gating circuit with timing consideration. We propose an efficient V-shaped framework which consists of a series of top-down splittings and bottom-up mergings. Experimental results reveal the effectiveness and the robustness of the proposed approach. Compared to the three top-performance teams in the 2011 CAD Contest, we achieve an 14.6% lower cost in average. Also, while the three teams fail to generate an solution when the timing constraint is hard to satisfy, we succeed in contrast.

並列關鍵字

clock gating ； timing consideration ； power ； clock network

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