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  • 學位論文

PC為基礎的軟體數位電視廣播接收器之數位降頻器設計和效能優化

Digital-Down-Converter Design and Optimization for PC-Based Software DVB-T Receiver

指導教授 : 曾恕銘

摘要


本文提出一個數位降頻器的新架構,用於PC為基礎的軟體數位電視廣播接收器中。我們令類比數位轉換器的取樣頻率為192/7MHz以及數位降頻器中的有限脈衝響應低通濾波器階數為7 (8個係數)。在數位降頻器運算部分提出一個CMF法來結合混波器以及濾波器,也就是預先將混波器以及濾波器結合在一起並將結果存成一個查詢表格。如此便可以省去混波器的運算處理。如果輸入數位降頻器的資料數為N個,所提出的CMF法只有2N個乘法。但是如果是之前沒有結合混波器及濾波器的架構則會有3N個乘法。最後,我們以組合語言來優化所提出的CMF法來滿足數位電視廣播即時播放的需求。

並列摘要


In this thesis, we propose a novel Digital-Down-Converter (DDC) architecture for PC-based software Digital Video Broadcasting-Terrestrial (DVB-T) receiver. We let A/D sampling rate be 192/7 MHz and the order of the lowpass FIR filter be seven (8 coefficients) in DDC. We then propose combining the mixer and filter (CMF), that is, pre-processing the mixer and filter coefficients and storing the results in a look-up table. If the input data of length N, the proposed CMF scheme has 2N multiplications but the previous architecture, which does not pre-process the mixer and filter coefficients together in advance, has 3N multiplications. Finally, we optimize our algorithm in assembly code to satisfy DVB-T real-time reception requirement.

並列關鍵字

DVB-T DDC Real-time

參考文獻


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