CMAC神經網路在半導體晶圓缺陷之辨識系統的設計

Design of CMAC Neural Networks for the Identification and Classification of Semiconductor Wafer Defects

戴士傑(Shih-Chieh Tai)

指導教授 ： 鍾雲恭

元智大學/工程學院/工業工程與管理學系/碩士(1998年)

摘要

半導體製程自動化的發展過程中，缺陷檢測自動化是相當重要的一環，因為相對於採用人工檢測方式，自動化的缺陷檢測系統具有以下優點：可以減少必須經過特殊訓練之檢視人工的需求、使人們不需從事枯燥且重複性的工作、利於保存與分析檢測資料以供管理決策、使檢測作業與生產排程能夠配合，並保持檢測水準的一致性與精確性，這些作業特性皆可以有效的提昇生產效率與降低生產成本；因此本文針對半導體晶圓（semiconductor wafer）較常發生的五種缺陷（短路、斷路、污點、氧化洞、突出物）建構一套缺陷辨識系統。首先透過紋路分析之灰階值共生矩陣法（gray-level co-occurrence matrix method）擷取出晶圓缺陷影像的紋路特徵，再利用CMAC（cerebellar model articulation controller）神經網路予以訓練學習而達到缺陷辨識之目的。經由實驗結果顯示由於CMAC神經網路具有區域性的歸納能力與快速的計算架構，使得CMAC神經網路在訓練上能夠快速收斂，且在缺陷辨識準確率方面亦有不錯的成效，非常適合線上即時檢測。

關鍵字

半導體晶圓 ； CMAC神經網路 ； 紋路分析 ； 灰階值共生矩陣

並列摘要

The automatic visual inspection is an important stage in the development of semiconductor manufacturing automation. It can greatly reduce the manual operation and training cots, decrease the tedious re-works, save the manufacturing data used as the information for manufacturing decision making and meet the production schedule with inspection activity in which the inspection quality including both consistency and accuracy is kept. Due to these advantages of the automatic visual inspection, this thesis investigates the five defects that may occur on the surface of a semiconductor wafer, short circuit, open circuit, spot, oxide hole, and inclusion, proposes a CMAC neural networks approach to inspect and identify the image of the five defects. Gray level co-occurrence matrices used in texture analysis are built up by the extraction of texture features of a defect wafer. A number of experiments show that the CMAC network is an appropriate tool, quick training and high accurate inspection rate, used on a real-time inspection production line.

並列關鍵字

semiconductor wafer ； CMAC neural networks ； texture analysis ； gray level co-occurrence matrix

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