隨著先進製程的演進,現今電子系統的設計瓶頸已不再是單一晶片中邏輯閘間的時間延遲,而逐漸演變成系統中晶片內所需的時間延遲與系統耗電量的考量,所謂的單晶片系統(System-on-Chip, SoC)設計也因此應運而生。 由於SoC的設計流程會依據系統需求規格將整個系統架構切分成許多子系統與各類功能元件,並分別以軟體或是硬體的方式來實現,透過圖形化的塑模語言來提升系統設計的抽象化層級將有助於系統設計者掌握整體系統架構及主要功能模組。雖然SystemC已提供數個抽象化層級來進行系統設計,且在每一個抽象化層級皆可以經由模擬與驗證來確保系統的正確性,但其終究是以程式碼的方式來呈現。藉由結合在軟體系統中被廣泛使用的統一塑模語言( Unified Modeling Language, UML )來進行以SystemC為基礎的SOC設計,將可以進一步地抽象化系統設計層級,也就是以UML提供的圖型元素來進行單晶片系統設計,以達成硬體/軟體協同設計的目的(HW / SW Co-design )。
As the manufacturing technology advances into the deep sub-micron era. Increasing demands for more performance have taken the system designs based on VLSI chips to their limits. The design bottleneck now is the interconnect delays and power consumptions rather than the basic gate delays. One way to eliminate the latency and power consumptions of accessing data external to the chip is putting all the various VLSI components into a single chip. It leads to the design paradigm of System-on-Chip (SoC), in which all the functionality of a complete system is put into a single silicon die, including both the software and hardware components. As the process of SoC design is getting more and more complicated, raising the abstraction layer can help system designers focus on the essential elements of the design. Since the SystemC language has already provided several layers of abstraction, systems to be constructed can initially be designed in the software-based un-timed functional models and further be refined to lower abstraction level to get the more detailed design. However, by the assistance of the United Modeling Language (UML), which is commonly used in designing software systems, the highest level of abstraction provided in SystemC can even be raised and the objective of the HW/SW Co-design can be achieved.
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