考慮共同路徑悲觀移除的漸進式時序分析

靜態時序一般用來驗證一個電路的時序，為了有效的考慮晶片上的變異，時序分析通常會使用「最快/最慢」分離的機制。然而，這樣的分離機制帶來了過度悲觀的情況，而導致時間測試得到錯誤的結果。「共同路徑悲觀移除̀」利用分析所有潛在問題的路徑，來移除這樣的悲觀，並且更正這些路徑上面的時序。另外，在最佳化的流程中，一個電路會經歷很多的指令修改，因此時序資訊可能被嚴重的影響。為了保持時序的一致性，快速且準確的時序更新技術成為一個重要的議題。這篇論文提出了一個修改過的時序模型圖，可以讓現有的共同路徑悲觀移除演算法，免除一個因為上升/下降分離而產生的額外所需時間。此外，我們也提出了一個漸進式時序分析架構，可以很有效的處理大量的電路修改指令。我們努力改善精準度，並且希望節省時間和記憶體使用量。實驗數據顯示我們的時序分析工具在以下三個方面皆勝過TAU 2015比賽的前兩名 (1) 1.58倍加速相對於iTimerC以及2.21倍加速相對於UI-Timer 2.0 (2) 精準度上的改善以及 (3) 更少的記憶體使用量。

關鍵字

共同路徑悲觀移除；漸進式時序分析；靜態時序分析

並列摘要

Static timing analysis is generally employed to verify the timing of a circuit. To effectively consider on-chip variations, early-late split mechanism is performed commonly. However, this split mechanism introduces unnecessary pessimism, which can mislead timing tests. Common path pessimism removal (CPPR) attempts to eliminate such pessimism by tracing those potentially problematic paths and correcting the timing information for those paths. During an optimization flow, a circuit could be modified by lots of operations and consequently the timing information has potential to be significantly affected. To keep timing information consistent for ensuring the timing closure, quickly and accurately updating timing information becomes a crucial issue. In this thesis, we propose a modified timing graph to avoid the existing CPPR algorithm proposed in [3] from suffering the extra penalties caused by rise/fall transitions spilt. Furthermore, we propose an incremental timing framework which is friendly on handling a large number of circuit modification operations. We make effort to promote the accuracy with saving runtime and memory usage. Experimental results show that our timer can outperform the winners of TAU 2015 contest by (1)1.58X speedup over iTimerC 2.0 and 2.21X speedup over UI-Timer 2.0, (2) accuracy improvement and (3) much less memory usage.

並列關鍵字

Common path pessimism removal ； Incremental timing analysis ； Static timing analysis

參考文獻

[9] T. W. Huang, P. C. Wu and M. D. F. Wong, "UI-timer: An Ultra-fast Clock Network

[1] Y. Kukimoto, M. Berkelaar and K. Sakallah, "Static Timing Analysis." Logic Synthesis and

[3] J. Bhasker and R. Chadha, "Static Timing Analysis for Nanometer Designs: A Practical

[4] TAU 2014 Contest: Common Path Pessimism Removal (CPPR),

[5] J. Hu, D. Sinha and I. Keller, "TAU 2014 Contest on Removing Common Path Pessimism

國際替代計量

考慮共同路徑悲觀移除的漸進式時序分析

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