An Efficient Phase Detector Positioning for Post-Silicon Clock Skew Minimization

針對後晶片時脈偏移最小化之有效率相差偵測器定位方法

林辰宇(Chern-Yeu Lin)

指導教授 ： 張世杰

國立清華大學/電機資訊學院/資訊工程學系/碩士(2009年)

摘要

時脈偏移最佳化已經成為晶片製造過程中一個很重要的課題。為了克服製程、電壓、溫度變異所造成的影響，自動時脈偏移同步方案可以在晶片製造出來之後動態地調整並降低時脈偏移。在自動時脈偏移同步方案中有兩個主要的元件，分別是可調變延遲緩衝器以及相差偵測器。之前的研究大部分強調可調變延遲緩衝器放置的位置。在這篇論文中，我們提出由於實際的可調變延遲緩衝器及相差偵測器設計上有其物理上的限制，相差偵測器連接正反器的拓墣也會影響最後的時脈偏移。在這篇論文中，我們首先分析給定相差偵測器架構下最糟的時脈偏移量。接著，我們提出一個能夠產生最小時脈偏移之相差偵測器架構的演算法。我們的實驗結果非常地振奮人心。

關鍵字

相差偵測器 ； 時脈偏移 ； 可調變延遲緩衝器

並列摘要

Clock skew optimization has been an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key components in a skew synchronization scheme: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous researchers emphasize on ADB placement issues. In this thesis, we show that how FFs are connected by PDs can also greatly influence the final clock skew due to limitations of a practical ADB and PD design. We first analyze the worst-case clock skew of PD connection structures. Then we propose an algorithm to generate an optimal PD connection structures resulting in the minimum clock skew. Our experimental results are very encouraging.

並列關鍵字

Phase Detector ； Clock Skew ； Adjustable Delay Buffer

參考文獻

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