應用於高碼率準循環低密度奇偶檢查碼使用降低錯誤平層技術之有效的分層解碼器架構

An Efficient Layered Decoder Architecture with Error-Floor Lowering Technique for High-Rate QC-LDPC Codes

周伯橋(Chou, Po Chiao)

指導教授 ： 翁詠祿

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

https://doi.org/10.6843/NTHU.2015.00557

摘要

在LDPC碼解碼時，有時會發生錯誤率並沒有隨著信噪比(Signal Noise Ratio)增加而明顯下降的情況，此種狀況稱之為錯誤平層現象(Error floor)。此現象主要是由LDPC碼中的特殊結構，陷阱組合(trapping sets)cite{Trap-Set}所造成的。對於儲存系統來說，高信噪比部分之性能非常重要。因此，如何降低錯誤平層便是一個很重要的課題。

目前已有許多方法透過分析陷阱組合資訊，有效的降低錯誤平層。但陷阱組合的分析需要很長的時間，且儲存陷阱組合資訊所需的硬體資源也是一個不可忽視的問題。本論文將透過現場可編輯邏輯閘陣列平台(Field-Programmable Gate Array，FPGA)觀察錯誤平層區域的錯誤型樣(Error pattern)，探討在工程上，如何快速且有效率的降低錯誤平層，並在硬體上能夠簡單、低複雜度的實現之演算法，並以FPGA進行驗證。

藉由分析錯誤型樣，我們可以取得對錯誤平層有重大影響的變數節點(variable node)區塊，我們稱之為有害區塊(harmful block)，如此便可省去進行陷阱組合分析的大量時間。此外，有害區塊較陷阱組合資訊所需儲存量來的小，因此在硬體實作上更加適合。根據FPGA之驗證結果，本論文提出之降低錯誤平層技術能夠有效的降低LDPC碼的錯誤平層。使其下降 2 ～ 2.5 個數量級。

關鍵字

錯誤更正碼 ； 錯誤平層

並列摘要

Extremely low error rate is required for storage systems.
Trapping sets are regarded as the major cause of the error floor of low-density parity-check (LDPC) codes.

In this work, a practical method is constructed for lowering the error floor of low-density parity-check (LDPC) codes.
At first, an hardware simulator is implemented using FPGA (Field-Programmable Gate Array),
and a large numbr of error samples can be collected along with the corresponding noise patterns.
Based on the correlations between the noise patterns and code structures,
the received bits can be cataloged and a table of {it harmful blocks} is listed.
When the error bits in the received sequence cannot be totally corrected using the formal decoding process,
the LLR values of certain bits are adjusted,
and a modified decoding process is excuted.
The selections of the adjusting bits are based on the harmful block table.

The total number of harmful blocks is equal to that of the block columns.
The storage for harmful blocks can be significantly reduced.
After sufficient error samples and noise patterns are collected,
it can be observed that only a small part of the harmful blocks is enough to achieve a satisfactory
error floor lowering capability,
and the storage requirement is small.
The proposed scheme has been evaluated with the assistance of the FPGA simulator,
and the error rate can be reduced to less than 1\% of the formal decoding process.

並列關鍵字

ECC ； LDPC ； Error floor

參考文獻

[21] Richard P. Brent, Paul Zimmermann, Algorithms for Finding Almost

[25] Youngjoo Lee, Jaehwan Jung and In-Cheol Park, Energy-scalable 4KB

[15] Chieh-Shen Hsieh, A Hardware-friendly Error-foor Lowering Technique

of low density parity check codes,Electron. Lett., vol. 32, no. 18, pp.

16451646, 1996.