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  • 學位論文

設計適用於千核心多核處理器之高效能晶片互連網路

Design a High Performance On-chip Interconnection Network for Thousand Many-core Architecture

指導教授 : 朱守禮
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摘要


半導體技術的持續演進,使得晶片可以擺放更多電晶體,在單一晶片上實現多顆處理器核心亦成為計算機結構主要發展方向。當核心數日益增加時,連結多個核心的互連網路即成為主要的效能瓶頸。由於IC製作方式的限制,傳統用於連結多個處理器的印刷電路板互連網路並不適用於晶片互連網路之用。有鑑於此,本論文提出了一個適用於多核心架構之新式晶片上互連網路架構︰Self Similar Cubic(SSC),並提出適用於SSC互連網路的連結方式、路徑選擇方式、交換器設計。相較於現有的晶片互連網路,如Mesh、Hypercube、Butterfly、Mesh-of-Trees以及Fat Tree等,SSC具有相當好的擴充性、晶片上的可實現性、與高傳輸效能等優點。在本論文中,首先以理論分析的方式,比較前述互連網路,與SSC的效能與成本差異。接著,並以實驗的方式,分析不同的傳輸模型下,SSC與其他互連網路的傳輸吞吐量差異。分析與實驗證明︰相較於其他互連網路,SSC可提供提供了較高Throughput及較低的硬體面積。與Mesh相比,其單位成本之效能可達5倍提升。此外,由於SSC互連網路的特性,在不修改交換器架構與路徑選擇方式下, SSC可支援千核以上的晶片多核心架構。

並列摘要


The continuous improving of semiconductor technology makes more transisters fill into a single chip. Integrating multilple processor cores into a single chip is also a main orientation of developing computer architectures. While integtate more and more cores into a chip, the interconnection network of all of the cores become a main performance bottleneck. Conventional PCB-based interconnection networks are not suitable for on-chip network. Accordingly, this paper provides a new on-chip interconnection network, Selt Similar Cubic (SCC), for many-core architectures. By cooperating with proposed linking mechanism, routing algorithm, and switching architectures, SSC has better scalability, on-chip fabrication possibility, and high communication performance, than conventional on-chip networks, such as Mesh, Hypercube, Butterfly, Mesh-of-Trees, and Fat Tree. In this paper, the theoretical analysis of peroformance and area cost are proposed. Than the pratical examinations of SSC with other networks under different communication patterns are provided. The analysis and experimental results reveal that SSC can provide higher throughput and lower area cost than other on-chip networks. The performance per area cost of SSC is five times better than that of Mesh. Since the capabilities of SSC, it can support more than thounand cores into a single chip without modifing the swich architecture and routing mechanism.

參考文獻


[15] L. E. Miller, “Connectivity Properties of Mesh and Ring/Mesh Network,”2001, [Online] Available at: http://w3.antd.nist.gov/wctg/netanal/MeshCon.pdf. [Accessed July 5, 2012].
[26] C. Wang, J. Zhang, X. Zhou, X. Feng, A. Wang, “A Flexible High Speed Star Network Based on Peer to Peer Links on FPGA,” Proceedings of Parallel and Distributed Processing with Applications (ISPA), 2011, pp. 107 - 112.
[1] J. L. Hennessy, D. A. Patterson, Computer Architecture – A Quantitative Approach, 4th edition, Morgan Kaufmann, 2007.
[5] G. E. Moore, “Cramming more components onto integrated circuits,” Proceedings of the Electronics Magazine, Volume 38, 1965.
[6] S. Murali, L. Benini, and G. D. Micheli, “An application-specific design methodology for on-chip crossbar generation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 7, Jul. 2007, pp. 1283 - 1296.

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