多重電壓與時序限制下整合時脈閘門和可調式緩衝器設計之研究

Integrating clock-gating and ADB insertion for timing fixing in multi-voltage design

郭少華(Shau-Hua Guo)

指導教授 ： 鄭維凱

中原大學/工學院/資訊工程研究所/碩士(2012年)

https://doi.org/10.6840/cycu201200510

摘要

在集成電路的低功耗設計上，多電壓模式和時脈閘門是兩種降低動態功耗常用的技術。多電壓模式藉由插入可調整延遲式緩衝器（ADBs）滿足時脈偏移的約束是一種有效的解決方案。此外，在時脈閘門技術中分裂閘門滿足時序約束是必須的技術。然而，插入的ADBs和閘門分裂會增加硬體成本。本文中，在時序約束和時脈偏移約束下，我們提出一種方法，同時降低硬體成本的ADBs和時脈閘門，並且與只插入ADBs、只分裂閘門和研究[2]做比較，實驗結果中表明我們的方法可以得到可行的解決方案，並有效地降低了硬體成本。

關鍵字

動態功耗 ； 時脈閘門 ； 多重電壓 ； 時脈偏移 ； 可調式緩衝器

並列摘要

In the low power design of integrated circuits, multi-voltage modes and clock gating are the two common techniques to reduce dynamic power consumption. To satisfy the clock skew constraint in the multi-voltage modes, adjustable delay buffers (ADBs) insertion is one of the promising solutions. In addition, gate splitting is necessary to satisfy the enable timing constraint for the clock gating technique. However, insertion of ADBs and gate splitting will increase the hardware cost. In this paper, under both the enable timing constraint and clock skew constraint, we propose a methodology to reduce the hardware cost of ADBs and clock gates simultaneously. In comparison with only ADBs insertion , clock gating only , or technique proposed by [2] is applied, experimental results show that our methodology can get feasible solution and reduce the hardware cost efficiently.

並列關鍵字

adjustable delay buffers(ADBs) ； clock skew ； dynamic power ； multi-voltage modes ； clock gating

參考文獻

[12] Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu , "Type-matching clock tree for zero skew clock gating," 45 th Design Automation Conference (DAC), pp. 714-719, June 2008.

[6] Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen, "Clock planning for multi-voltage and multi-mode designs," 12th International Symposium on Quality Electronic Design (ISQED), pp.1-5, March 2011.

[24] Xin Zhao, Tolbert, J.R., Chang Liu, Mukhopadhyay, S., Sung Kyu Lim, "Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits," International Symposium on Low Power Electronics and Design (ISLPED), pp. 9-14, Aug. 2011.

[8] Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang, "Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1921-1930, Dec. 2010.

[1] 2011 CAD Contest Website :