三維積體電路之不同溫度分佈下最小時序差異時鐘樹

三維晶片是將一個大型的二維平面電路分割成數塊，透過矽穿孔將數個區塊垂直堆疊起來的技術，相較傳統的二維平面晶片，可有效的減少面積與總線長，但相對以垂直堆疊的方式會導致散熱不易，越上層所累積的熱也越高，即使線段等長，但在每一層所造成的時序延遲卻是截然不同的。因此如何在不同溫度分佈的晶片上，構建出最小時序差異的時鐘樹已成為一個重要的議題，在本篇論文，我們提出了在最高的溫度分佈下的環境，和溫度均勻分佈的環境下，所造成的時序差異能達到近乎相同。從實驗結果可證明，我們演算法所建構出來的時鐘樹，能減少在最高溫與均勻的溫度分佈環境下的時序差異、矽穿孔數量與總線長，並同時達到兩者近乎相同的時序差異。首先讀入晶片各層溫度分佈的情況，使用Delay-based Sink Relation Graph演算法建立各點的連線關係。接著以Delay-based的Grouping方法，挑選較小delay的組合先合併。挑選出的組合，在考慮溫度分佈下，找到Merging Segment的位置，再回到Delay-based Sink Relation Graph演算法建立新的連線關係，直到只剩一個尚未合併的點為止。最後依據時鐘樹拓墣的架構，由Source到樹根再到其child nodes，在各個Merging Segment上找到離其parent最近點，完成時鐘樹的建立。

關鍵字

溫度；三維晶片；時序差異

並列摘要

3D IC integration of circuit is a promising approach to integrate large systems on a single chip. The average global wirelength is reduced drastically. But the thermal can not dissipate efficiently in 3D ICs, because each chips are stacked in vertical direction. The temperature in 3D ICs increase drastically. Therefore, how to construct a minimal skew clock tree considering the temperature distribution is becoming an important issue. In this parper, we proposed a 3D clock tree generator that the skew under worst case temperature profile and uniform temperature profile are nearly equal. Experimental results show that our algorithms significantly reduce the skew and balance clock skew values under different temperature profiles. First, we import the temperature distribution of a chip before we construct the clock tree. We build sink relation by Delay-based Sink Relation Graph algorithm, and choose smaller delay by Delay-based Grouping. We will calculate the precise position of Merging Segments according to the temperature at each tile. Finally, we build up the thermal-aware clock tree in top down phase with the information of the topology.

並列關鍵字

skew ； temperature ； 3D IC

參考文獻

[9] 吳翊銘,”三維積體電路之熱導向時鐘樹構建,”中原大學資訊工程研究所碩士論文, 2010.

[6] Dhar, Franklin, Wang,” Reduction of clock delays in VLSI structure,” in Proceedings of ICCD,1984.

[1] A. Rahman, D. Antoniadis, and A. Agarwal, “System Level Performance Evaluation of Three-Dimentional Integrated Circuits,” in IEEE Transactions on VLSI Systems, vol. 8, pp. 671–678, December 2000.

[2] R. H. Havemann and J. A. Hutchby, “High-Performance Interconnects: An Integration Overview,” in Proceedings of IEEE, vol. 89, pp. 586–601, May 2001.

[3] H. Kurino et. al., “Intelligent Image Sensor Chip with Three Dimensional Structure,” in Proceedings of International Electron Devices Meeting (IEDM), pp. 879–882, 1999.

國際替代計量

三維積體電路之不同溫度分佈下最小時序差異時鐘樹

全文下載

主題瀏覽