本論文利用電感耦合電漿蝕刻和感測元件製程,製作具有微米級結構之電解質-絕緣層-半導體感測元件,並且探討感測薄膜以及結構對元件特性之影響。 在實驗結果中,我們發現使用50 nm的氧化層的EIS有較好的遲滯,成長了APTES的EIS感測元件靈敏度、遲滯或著是時漂都能有顯著的改善,此外,利用在微米級結構能提升感測元件特性。
In this thesis, the Electrolyte-Insulator-Semiconductors with microscale structures were fabricated by inductively coupled plasma etching. In our results, the hysteresis of sensor was improved with the 50 nm SiO2 sensing membrane. The sensitivity, hysteresis, and drift of EIS with the APTES/SiO2 stacked sensing membrane were all improved. Finally, with the micron-scale structures, the characteristics of sensors were all improved.