This article provides a method to significantly improve breakdown voltage and specific on-resistance in high resistivity drift region LDMOS by using PBL doping under the source terminal and the gate extended field plate technologies. The insertion of PBL aims at the reduction of bulk current caused by the impact-ionization-generated holes while the gate extended field plate will shift the impact ionization region from N-drift region surface near the gate side down towards the junction between the P-body and N-drift region and thereby increase the breakdown voltage due to the increase of maximum depletion in the N-drift region.
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