本文主要研究單根蛇形延遲線應用在高速數位電路板上不同繞線方式對訊號完整度的影響。本文將針對幾個實際應用的例子,模擬其結構並針對不同的結構圖中主要的信號雜訊來源進行分析,其主要雜訊來源是傳輸線間的串音雜訊干擾,經由建立結構圖後再利用不同的參數變化及繞行走線方式量測幾個重要的參數進行分析比較,參數例如時域穿透波形TDT、時域反射波形TDR及眼圖…..等等的模擬結果分析取得有效的資訊。經由實驗應用到數位電路板上進行實體量測,最後利用模擬後的結果與實體實驗的結果來確認模擬與理論的驗證差異。
This article is about the study of different wiring methods’ signal effectiveness of serpentine delay line’s application on the high-speed digital circuits. This study based on the analysis of primary signals simulated in several structural differences in different diagrams of actual applications. The main source of statics is crosstalk between transmission lines. After establish diagram and than obtain effective data by comparing measurements of major factors such as time domain reflectometry (TDR) and time domain transmission (TDT), and Eye Diagram. Through applying the experimental analysis to high-speed digital circuits and finally field tested to confirm variations between simulations and the actual field test.