藉由回收老化引起的時鐘偏差改善電路可靠度

Making Aging Useful by Recycling Aging-Induced Clock Skew

曾天鴻(Tien-Hung Tseng)

指導教授 ： 吳凱強

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2018年)

摘要

電子元件老化使得電路性能和壽命顯著損失，這是使電子元件可靠性降
低的主要因素。在這篇論文中，我們建議通過操縱和回收這些時變偏斜來
利用老化引起的時鐘偏差（意即，使電路能容忍更多老化），藉以補償因老
化導致的邏輯電路之性能下降。我們的目標是在電路中分配可實現/合理的
老化引起的時鐘偏差，使得可以容忍由於老化導致的性能下降，(意即，可
以最大化電路壽命)。藉由實驗，平均可以達到24.95％老化耐受性。此外，
我們在時鐘緩衝器上採用Vth 分配，以進一步容忍老化引起的邏輯電路效能
降級。當Vth 分配應用於上述老化操作之上時，平均老化耐受性可以提高到
37.61％。

關鍵字

老化 ； 可靠度

並列摘要

Device aging, which causes significant loss on circuit performance and lifetime,
has been a primary factor in reliability degradation of nanoscale designs. In this paper,
we propose to take advantage of aging-induced clock skews (i.e., make them
useful for aging tolerance) by manipulating and recycling these time-varying skews
to compensate for the performance degradation of logic networks. The goal is to
assign achievable/reasonable aging-induced clock skews in a circuit, such that its
effective performance degradation due to aging can be tolerated, that is, the lifespan
can be maximized. On average, 25.04% aging tolerance can be achieved with insignificant
design overhead. Moreover, we employ Vth assignment on clock buffers
to further tolerate the aging-induced degradation of logic networks. When Vth assignment
is applied on top of aforementioned aging manipulation, the average aging
tolerance can be enhanced to 35.96%.

並列關鍵字

Aging ； Reliability

參考文獻

[1] (2015). International technology roadmap for semiconductor.

[2] Amrouch, H., Khaleghi, B., Gerstlauer, A., and Henkel, J. (2016). Reliability-aware design to suppress aging. In Proceedings of the Design Automation Conference, pages 1–6.

[3] Chakraborty, A. and Pan, D. Z. (2013). Skew management of nbti impacted gated clock trees. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(6):918–927.

[4] Chakravarthi, S., Krishnan, A., Reddy, V., Machala, C., and Krishnan, S. (2004). A comprehensive framework for predictive modeling of negative bias temperature instability. In Proceedings of the International Reliability Physics Symposium, pages 273–282.

[5] Chen, J. and Tehranipoor, M. (2013). A novel flow for reducing clock skew considering nbti effect and process variations. In Proceedings of the International Symposium on Quality