供電限制下之多通道固態硬碟動態電流控制策略

快閃記憶體儲存裝置因為高效能、抗震性、低功耗等特性，固態硬碟逐漸取代傳統硬碟作為主要儲存裝置。然而，為了進一步提升效能與容量，廠商傾向於採用多通道架構，雖然增加了整體平行度，但也使得裝置耗電提高，若不小心處理，固態硬碟峰值電流將超越傳統硬碟，低功耗將不再是快閃記憶體的優勢，除此之外，當峰值電流超越儲存裝置介面提供之功率預算，會使得裝置無法全速運作，造成效能損失。本研究我們提出動態控制峰值電流之排程演算法，首先透過實際量測建立出各種快閃記憶體操作之功耗，接著根據數學定理提出能有效控制峰值電流的排程演算法。相較於過去研究提出之基於個數之排程演算法，我們的演算法能達到更高的吞吐量。此外，現今快閃記憶體採用多階層儲存單元(Multi-layer cell)快閃記憶體，其成對頁(paired pages)彼此寫入速度以及功耗不相同，我們利用此特性提出減少裝置反應時間之寫入策略。

關鍵字

固態硬碟；峰值電流；功耗預算；功耗模型；排程演算法；寫入策略

並列摘要

Flash memory based storage has become more and more popular for its high performance, shock resistance, and power efficiency. Solid-state disks are replacing HDDs as the main storage devices. However, in order to achieve better throughput and larger capacity, the manufacturers adopt the multichannel architecture consisting of multiple flash chips. As a result, the power consumption grows up with the degree of parallelism. Despite achieving higher performance, the peak power consumption issue becomes a problem. With limited power supply provided by the interface ports, the devices may suffer performance degradation. In this work we proposed a dynamic current capping (DCC) algorithm to enforce the power budget without sever performance degradation. We first build the power models of flash operations from empirical measurement. Then we design the algorithm based on mathematical corollary. The results show that our algorithm outperforms the traditional count-based algorithms. In addition, we exploit the asymmetry of MLC flash paired pages to propose a writing strategy improve the device response time.

並列關鍵字

Solid-state disks ； peak power ； power budget ； power model ； scheduling algorithm ； writing strategy

參考文獻

[22] Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, and Rakesh Kumar. 2009. Reducing peak power with a table-driven adaptive processor core. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture （MICRO 42）. ACM, New York, NY, USA, 189-200.

[13] Jinha Park , Sungjoo Yoo , Sunggu Lee , Chanik Park, "Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems," Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems, p.24-35, November 16-18, 2009

[17] Tzu-Jung Huang; Chien-Chung Ho; Po-Chun Huang; Yuan-Hao Chang; Che-Wei Chang; Tei-Wei Kuo, "Current-aware scheduling for flash storage devices," Embedded and Real-Time Computing Systems and Applications (RTCSA), 2014 IEEE 20th International Conference on , vol., no., pp.1,10, 20-22 Aug. 2014

[8] Seokhei Cho, Youjip Won, Sooyong Kang, Jaehyuk Cha, Jongmoo Choi and Sungroh Yoon, "Influence of Number of Channels and FTL on SSD Power Consumption," in Proceedings of 2012 International Conference of Electrical, Computer, Electronics and Biomedical Engineering （ICECEBE2012）, Bangkok, Thailand, December 2012.

[9] Seokhei Cho, Changhyun Park, Youjip Won, Sooyong Kang, Jaehyuk Cha, Sungroh Yoon, and Jongmoo Choi. 2015. Design Tradeoffs of SSDs: From Energy Consumption’s Perspective. Trans. Storage 11, 2, Article 8 (March 2015), 24 pages

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供電限制下之多通道固態硬碟動態電流控制策略

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