電力系統之輸電線故障電流常含有大量指數衰減直流成份,易造成比流器飽和而引起二次側電流扭曲,進而使數位保護電驛誤動作或動作延遲。本文針對實驗室所發展的比流器飽和電流修正演算法提出FPGA實現,演算法中使用離散小波轉換萃取特徵以判定比流器飽和發生,此後,藉由比流器無飽和時之電流取樣值,使用最小平方誤差法以估測電流之數學模型參數,可於比流器飽和時以波形合成方式產生電流波形以修正飽和電流。本文中設計此演算法之RTL硬體架構並使用VHDL建模,此後以Matlab/Simulink 模擬器所產生的測試向量進行合成前VHDL模型的功能模擬驗證,此後將所設計之VHDL模型合成於FPGA,並進行合成後的功能模擬驗證與時序分析,結果顯示所設計之FPGA功能正確且時脈最大頻率符合即時性應用之計算速度要求。
The fault currents caused by transmission line faults in power system contain considerable exponentially decaying DC offset. Meanwhile, the CT tends to saturation due to DC offset, and the secondary current is distorted when CT saturation occurs. Such saturation current gives rise to mal-operation or delayed trip in digital protection relays. In this thesis, a FPGA realization of the algorithm developed in our laboratory for correction of CT saturation current is proposed. In the developed algorithm, Discrete Wavelet Transform is used to extract the features in a CT current for identifying the occurrence of CT saturation. Thereafter, the samples of unsaturated current are used to estimate the parameters of the mathematic model of secondary current through Least Square Error method. Furthermore, the estimated parameters are utilized to synthesize the current waveform for correcting the saturated current during the period of CT saturation.The RTL hardware architecture of this algorithm is designed and further modeled by VHDL is presented in this thesis. And, pre-synthesis simulation is performed for functional verification by using test vectors generated from Matlab/Simulink simulator. Afterward, the presented VHDL model is synthesized into FPGA. Then, functional verification and timing analysis is also performed for the post-synthesis model. The results show that the function of designed FPGA is correct and the maximum frequency of clock meets the requirement of computation speed for real-time application.
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