應用於記憶體具裕度增強及臨界電壓補償架構之小偏移電壓感測放大器

A Small Offset Voltage Sense Amplifier with Margin Enhancement and Threshold Voltage Compensated Schemes for Memories

洪睿渝(Hung, Jui Yu)

指導教授 ： 張孟凡

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

https://doi.org/10.6843/NTHU.2015.00400

摘要

近年來，非揮發性記憶體普及性高並且應用極廣，其中快閃記憶體因為提供了低成本與高容量的儲存空間，成了非揮發性記憶體中的主流。然而，快閃記憶體需要高電壓與長時間來進行寫入抹除；更糟的是，快閃記憶體在製成微縮下遇到了許多挑戰，像是低儲存單元電流、高偏移臨界電壓與耦合雜訊干擾。相較起來，新興非揮發式記憶體能有效減緩這些問題，並且具有潛力取代快閃記憶體成為下世代的主流非揮發性記憶體。
接觸點電阻式記憶體(Contact ReRAM)具有較低的寫入電壓與較快的寫入時間，並且相容於CMOS邏輯製成。這些特性使接觸點電阻式記憶體對於產業界來說極具吸引力。然而，接觸點電阻式記憶體受困於小阻值率及阻值高偏移問題，再加上CMOS邏輯製成本身的偏移問題，提高了正確讀取記憶單元的困難度。為了改善記憶體系統之讀取速度與良率，我們提出了具裕度增強及臨界電壓補償架構之小偏移電壓感測放大器，我們透過臨界電壓補償架構使偏移量在1V降低了69%，於0.5V降低了63.8%。裕度增強架構提升裕度高達3.7倍的效果。以上兩種架構，使我們的感測放大器可以有效減少位元線電壓發展時間，覆蓋4個標準差的整體速度提升了約30%，壓差輸入僅需20mV即可覆蓋4個標準差的偏移量。
我們在非揮發性內容遁址記憶體(nvTCAM)實現我們的感測放大器，此案於台積電65奈米標準CMOS製成下製作。藉由我們的小偏移感測放大器，量測非揮發性內容遁址記憶體之讀取時間可以達到1.2ns。

關鍵字

感測放大器 ； 小偏移

並列摘要

In recent years, non-volatile memory is popular and used in many applications. Among them, Flash memory is the mainstream of non-volatile memory, because it provides low-cost and high capacity storage. However, Flash memory demands high program/erase voltage and long program/erase time. Even worse, Flash memory faces many challenges in scaling technology, such as small cell current, large variation of threshold voltage and coupling noise. On the other hand, emerging non-volatile memory can alleviate those concerns, and has the potential to replace Flash memory in the next generation of mainstream non-volatile storage.
CRRAM performs lower program voltage and fast program time with CMOS logic process compatible. These characteristics make CRRAM attractive to industry. Nevertheless, CRRAM suffers from small R-ratio and variation of resistance. Plus the variation of CMOS logic process, it is difficult to sense the memory cell correctly. In order to improve sensing speed and yield of a memory system, we propose a small offset sense amplifier with margin enhancement and threshold voltage compensated schemes. The offset suppression of the proposed sense amplifier is about 69% at 1V and 63.8% at 0.5V by our threshold voltage compensated scheme. The margin enhancement scheme can overall achieve 3.7 times enhanced efficiency. With these two schemes, the sensing speed under 4-Sigma is improved about 30% due to reduced BL developing time. As for yield, the proposed SA only require 20mV input difference to cover 4-Sigma variation.
We implement our proposed SA into an nvTCAM macro fabricated in TSMC 65nm CMOS process. The measured read access time can achieve 1.2ns by our proposed SA.

並列關鍵字

sense amplifier ； small offset

參考文獻

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