軟體化延遲鎖定迴路之研究與實作

延遲鎖定迴路具有消除時脈歪斜的功能，目前已被廣泛應用於各種系統的同步電路，用以提供一個穩定的系統時脈。本篇論文提出了可使用軟體來控制並達到相位鎖定的軟體定義之延遲鎖定迴路平台(SDDLL)。此平台同時具有消除時脈歪斜、多相位的時脈輸出以及工作週期校正等功能，以WISHBONE bus結合了OPENRISC的or1200 CPU以及全數位式延遲鎖定迴路的數個IP。CPU可以進行軟體指令的執行與運算，在平台的應用以及規格改變時，只需要修改軟體便可符合規格，避免掉重新設計硬體的流程，減少時間及金錢的消耗，提升了重複利用度以及彈性。此平台所有的矽智財是建立在TSMC65nm GP 1P6M製程下，軟體部分則是使用gcc以及GNU toolchain來實作。

關鍵字

軟體定義之延遲鎖定迴路；相位鎖定

並列摘要

Delay-locked loop can do clock deskew, and it is widely applied to the synchronous circuits on various hardware systems nowadays. It can provide a stable system clock. In this paper, a software-controllable and phase-lockable platform of software-defined delay-locked loop(SDDLL) is proposed. This platform can do clock deskew, multiphase output clock and duty cycle calibration. It is combined of OPENRISC or1200 CPU and several intellectual properties in all-digital delay-locked loop. CPU can execute the software instructions and do many operations. When the application or specification of the platform is changed, it only needs to modify the software and the platform still meet the new specification. The DLL can avoid the procedure of the hardware redesign, so the verification of locking strategy can be faster due to the reusability and the flexibility of software. All of the silicon IPs of the platform are fabricated in TSMC65nm GP 1P6M process, And the software are implemented by gcc and GNU toolchain.

並列關鍵字

SDDLL ； Phase-locking

參考文獻

[5] Chang-Ying Chuang, Terng-Yin Hsu” The Study of Software-defined Phase-locked loop ” Thesis CS, NCTU 2008.

[1] Terng-Yin Hsu, Wei-Chi Lai, Yuan-Te Liao “A Cost-Effective Preamble-Assisted Engine with Skew Calibrator for Frequency-Dependant I/Q Imbalance in 4x4 MIMO-OFDM Modem”

[2] Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee ”An all-digital phase-locked loop(ADPLL)-based clock recovery circuit” Solid-State Circuits, IEEE Journal of Volume 34, Issue 8, Aug. 1999 Page(s):1063-1073

[3] Ching-Che Chung, Chen-Yi Lee “A New DLL-Based Approach for All-Digital Multiphase Clock Generation” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, MARCH 2004

[10] Rong-Jyi Yang, Shen-Iuan Liu “A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 2, FEBRUARY 2007

國際替代計量

軟體化延遲鎖定迴路之研究與實作

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