超薄氧化層金氧半電容元件之製程開發與特性分析

由於元件的微縮，超薄閘氧化層在今日逐漸成為主流。在本論文中，探討金氧半電容元件超薄閘氧化層的製程開發與特性分析。在論文的第二章，探討在金氧半電容元件矽與二氧化矽介面殘餘離子與氣體對超薄閘氧化層特性的影響。我們提出一個新的製程步驟：常溫真空步驟去探討對此介面的影響。在生長完氧化層後將操作試片置於常溫低壓氮氣環境一段時間，討論其二氧化矽的厚度、平帶電壓的偏移量、介面陷阱密度、電容電壓特性圖以及漏電流的變化。在論文的第三章則可分成兩個部分，第一部分為超薄閘氧化層厚度的萃取。相較於傳統的平帶電壓，我們在此提出氧化層平帶電壓。藉由氧化層平帶電壓的電流密度對閘氧化層厚度做圖的延伸線，超薄閘氧化層的厚度將更容易萃取。在第二部分，探討金氧半電容元件的記憶體現象。經過正負偏壓一段時間後，在弱反轉區可以得到高低兩個電流與電容狀態。此現象是藉由氧化層閘極邊緣的氫氧根離子受負正偏壓排斥與吸引所造成。由於材料與製程極為簡單，希望在不久的將來可以應用於記憶體元件之中。

關鍵字

金氧半電容；超薄氧化層；製程

並列摘要

Process development and the characterization of MOS capacitor with ultra-thin oxide were explored in this thesis for the ultra-thin gate oxide becomes the mainstream nowadays. The influence of residual ions and gases at the Si/SiO2 interface in metal-oxide-semiconductor (MOS) structure was investigated in chapter 2. A new processing step, room temperature (RT) vacuum treatment, was proposed to study the influence of them on the characteristics of the interface. Treatment sample was placed under low nitrogen pressure at room temperature after oxidation but before post-oxidation annealing (POA). The oxide thicknesses, flat-band voltage (VFB) shifts, interface trap densities (Dit), capacitance-voltage (C-V) characteristics, and leakage current were discussed between the treatment and control samples. There were two parts in chapter 3. In the first part, a new methodology to extract ultra-thin gate oxide thickness was proposed. Oxide flat-band voltage (VOX, FB) was well defined in this study as compared with the conventional VFB. Based on the current density at VOX, FB obtained from the experimental data and the plotted natural logarithm of current density at VOX, FB versus oxide thickness, ultra-thin oxide layer thickness can be extracted easily. In the second part, MOS capacitor memory phenomenon was studied. After applying -2.5 V and +2.5 V for a while, there are two current states in the I-V curves and two capacitance states in the C-V curves of weak inversion region by the repelling and recovery of OH- at the edge of gate electrode in oxide layer. Due to existing of two states current and capacitance, there is a capability for this device to be applied to memory device in the future.

並列關鍵字

MOS Capacitor ； Ultra-thin Oxide

參考文獻

[19] P. F. Schmidt, T. W. O’Keeffe, J. Oroshinik and A. E. Owen, “Doped Anodic Oxide Films for Device Fabrication in Silicon: Diffusion Source of Controlled Composition and Diffusion Resultsm,” J. Electrochem. Soc., Vol. 112, pp. 800-807, 1965.

[3] D. A. Muller, T. Sorsch, S. Moccio, S. Moccio, F. H. Baumann, K. Evans-Lutterodt and G. Timp, “The Electronic Structure at the Atomic Scale of Ultrathin Gate Oxides,” Nature, London, Vol. 399, pp. 758-761, 1999.

[4] D. A. Muller, Nature Materials,” A sound barrier for silicon?,” Vol. 4, pp. 645-647, 2005.

[5] The International Technology Roadmap for Semiconductors, 2009.

[6] D. A. Buchanan, “Scaling the Gate Dielectric: Materials, Integration and Reliability,” IBM J. Res. Dev., Vol. 43, pp. 245-246, 1999.

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超薄氧化層金氧半電容元件之製程開發與特性分析

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