考慮線長比例匹配之類比電容矩陣繞線

Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits

曹蕙芳(Hui-Fang Tsao)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.10896

摘要

對於交換式電容電路 (switched-capacitor circuit) 而言，效能主要受到電容比例匹配度所影響。因此，許多利用交換式電容電路來實現的類比電路，也就會受到電容比例匹配度影響電路品質。文獻主要集中在如何擺放這些單位電容，使其可以抵抗製程變異造成的系統不匹配和隨機不匹配。然而，在先進的積體電路設計中，繞線所造成的寄生電容效應已不容忽視，也就是說將這些單位電容做繞線也會影響整體電容比例的匹配度。本論文提出一個線長比例匹配的電容繞線演算法來解決線長比例匹配的問題 (length ratio matching problem)，目的是要將這些繞線的線長比例可以符合所需的電容比例。此演算法包含兩個主要步驟：(1)產生拓樸 (topology generation)；(2)繞線 (routing)，並且是率先考慮線長比例匹配問題的繞線方法。實驗中將本演算法和兩個不同方法比較，對於較小測試資料，兩個比較方法所需的平均成本分別為本演算法所需的1.62 倍和 2.65 倍；對於較大測試資料，則是分別為1.34 倍和1.16 倍。此外，對所有的測試資料只有本演算法能夠成功地完成繞線。

關鍵字

實體設計 ； 電容矩陣電容擺置 ； 交換式電容電路 ； 寄生效應

並列摘要

The key performance of switched-capacitor circuits would be degraded by capacitance ratio mismatch. Accordingly, the quality of the analog integrated circuits which are realized with switched-capacitor circuits is also influenced by the capacitance ratio mismatch. Several precious works focused on the capacitor placement to reduce systematic mismatch and random mismatch from process variation. However, as the technology node advances into the nanometer era, the parasitic effects of interconnects on the layout with multiple unit capacitors cannot be ignored and will contribute to the capacitance, thus changing the capacitance ratio. In this thesis, we propose a length-ratio-matching routing for capacitor interconnects that solves the length ratio matching problem (LRMP). The purpose is to route unit capacitors such that the wirelength ratio can be set to match the desired capacitance ratio. Our proposed two-stage approach of topology generation followed by routing, named topology-guiding based routing technique, is the first work that addresses the wirelength ratio issue in capacitor arrays. The experimental results show that two compared methods lead to averagely 1.62X and 2.65X cost over our algorithm for small cases, and averagely 1.34X and 1.16X cost over our algorithm for large cases. In addition, only our algorithm can successfully solve the LRMP for all cases.

並列關鍵字

physical design ； capacitor array ； capacitor placement ； switched-capacitor circuit ； parasitic effect of interconnects

參考文獻

[18] J. Lou, S. Krishnamoorthy, and H. S. Sheng, “Estimating routing congestion using probabilistic analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 32--41, January 2002.

[9] A. Hastings, The Art of Analog Layout. Prentice Hall, 2000.

[1] P. M. Aziz, H. V. Sorensen, and J. V. Spiegel, “An overview of sigma-delta converters,” IEEE Signal Processing Magazine, vol. 68, no. 1, pp. 61--84, January 1996.

[2] L. Baldi, B. Franzini, D. Pandini, and R. Zafalon, “Design solutions for the interconnection parasitic effects in deep sub-micron technologies,” Microelectronic Engineering, vol. 55 (1-4), pp. 11--18, March 2001.

[3] A. Boser and B. A. Wooley, “The design of sigma-delta modulation analog-to-digital converters,” IEEE Journal Solid-State Circuits, vol. 23, no. 6, pp. 1298--1308, December 1988.