比流器飽和電流修正演算法與FPGA實現

Algorithm for Correction of CT Saturation Current and Its FPGA Realization

陳佳明(Chya-Ming Chen)

指導教授 ： 林穎宏

長榮大學/管理學院/經營管理研究所(博)/碩士(2008年)

https://doi.org/10.6833/CJCU.2008.00167

摘要

電力系統之輸電線故障電流常含有大量指數衰減直流成份，易造成比流器飽和而引起二次側電流扭曲，進而使數位保護電驛誤動作或動作延遲。本文針對實驗室所發展的比流器飽和電流修正演算法提出FPGA實現，演算法中使用離散小波轉換萃取特徵以判定比流器飽和發生，此後，藉由比流器無飽和時之電流取樣值，使用最小平方誤差法以估測電流之數學模型參數，可於比流器飽和時以波形合成方式產生電流波形以修正飽和電流。本文中設計此演算法之RTL硬體架構並使用VHDL建模，此後以Matlab/Simulink 模擬器所產生的測試向量進行合成前VHDL模型的功能模擬驗證，此後將所設計之VHDL模型合成於FPGA，並進行合成後的功能模擬驗證與時序分析，結果顯示所設計之FPGA功能正確且時脈最大頻率符合即時性應用之計算速度要求。

關鍵字

比流器飽和電流修正 ； RTL硬體架構 ； FPGA ； VHDL

並列摘要

The fault currents caused by transmission line faults in power system contain considerable exponentially decaying DC offset. Meanwhile, the CT tends to saturation due to DC offset, and the secondary current is distorted when CT saturation occurs. Such saturation current gives rise to mal-operation or delayed trip in digital protection relays. In this thesis, a FPGA realization of the algorithm developed in our laboratory for correction of CT saturation current is proposed. In the developed algorithm, Discrete Wavelet Transform is used to extract the features in a CT current for identifying the occurrence of CT saturation. Thereafter, the samples of unsaturated current are used to estimate the parameters of the mathematic model of secondary current through Least Square Error method. Furthermore, the estimated parameters are utilized to synthesize the current waveform for correcting the saturated current during the period of CT saturation.The RTL hardware architecture of this algorithm is designed and further modeled by VHDL is presented in this thesis. And, pre-synthesis simulation is performed for functional verification by using test vectors generated from Matlab/Simulink simulator. Afterward, the presented VHDL model is synthesized into FPGA. Then, functional verification and timing analysis is also performed for the post-synthesis model. The results show that the function of designed FPGA is correct and the maximum frequency of clock meets the requirement of computation speed for real-time application.

並列關鍵字

Correction of CT saturation current ； RTL hardware architecture ； FPGA ； VHDL

參考文獻

[6] 陳嘉鴻，『比流器飽和偵測與飽和電流修正技術之研究』，長榮大學經研管理研究所碩士論文，民國九十六年。

[5] IEEE C37.111-l996, "IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power Systems", 1996.

[7] ”Requirement for instrument transformer”, C57.13-1993 ANSI/IEEE Standard.

[8] ”IEEE Guide for the Application of Current Transformers Used for Protective Relaying Purposes”, IEEE Std C37.110-1996.

[11] Y. C. Kang, S. H. Ok, S. H. Kang, “A CT Saturation Detection Algoruthm,” IEEE Transactions on Power Delivery, vol. 19, No. 1, pp. 78–85, Jan. 2004.