stands for Digital Object Identifier
and is the unique identifier for objects on the internet. It can be used to create persistent link and to cite articles.
Using DOI as a persistent link
To create a persistent link, add「http://dx.doi.org/」
before a DOI.
For instance, if the DOI of an article is 10.5297/ser.1201.002 , you can link persistently to the article by entering the following link in your browser: http://dx.doi.org/ 10.5297/ser.1201.002 。
The DOI link will always direct you to the most updated article page no matter how the publisher changes the document's position, avoiding errors when engaging in important research.
Cite a document with DOI
When citing references, you should also cite the DOI if the article has one. If your citation guideline does not include DOIs, you may cite the DOI link.
DOIs allow accurate citations, improve academic contents connections, and allow users to gain better experience across different platforms. Currently, there are more than 70 million DOIs registered for academic contents. If you want to understand more about DOI, please visit airiti DOI Registration （ doi.airiti.com ） 。
- . G. H. Loh and M. D. Hill, “Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches”, in IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 454-464, 2011.
- . G. H. Loh and M. D. Hill, “Supporting Very Large DRAM Caches with Compound Access Scheduling and MissMaps”, in IEEE Micro Magazine, Special Issue on Top Picks in Computer Architecture Conferences, 2012.
- . M. K. Qureshi and G. H. Loh, “Fundamental Latency Trade-offs in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design”, in 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 235-246, 2012.
- . T. Ono, K. Inoue, and K. Murakami, “Adaptive Cache-Line Size Management on 3D Integrated Microprocessors”, in SoC Design Conference, pages 472-475, 2009.
- . F. Hameed, L. Bauer, and J. Henkel, “Simultaneously Optimizing DRAM Cache Hit Latency and Miss Rate via Novel Set Mapping Policies”, in International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2013.
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