應用於家庭監控系統之窄頻電力線通訊傳收機設計

Narrow Band Power Line Communication Transceiver Design for Household Control Systems

黃穎聰(Ying-Cong Huang) ； 張峰銘(Feng-Ming Chang) ； 陳信文(Xin-Wen Chen)

《興大工程學刊》 22卷1期 (2011/06) Pp. 1-22

https://doi.org/10.6287/JENCHU.2011.2201.01

摘要

本論文係針對「智慧型室內電力監控系統」之應用，設計出一個低複雜度的電力線通訊數據機，作為網路內資料與控制訊號傳輸之工具。首先建立了電力線通訊的通道模型，加入了有色背景雜訊、窄頻雜訊、脈衝雜訊三種主要雜訊型態，再以傳輸位元錯誤率的模擬來驗證各種電力線通訊調變方法之選擇。經模擬驗證後，所提出數據機是採直接序列展頻的M路雙正交鍵移以及頻率鍵移的兩階段調變。前者係採用修正型華氏碼來降低傳統型華氏碼的自相關性函數之旁葉，以提供更好的偵測效果。而後者主要是對抗電力通道上嚴重的雜訊與訊號衰減問題。此外針對十六組修正型華氏正交碼，採用了八路並行的符號偵測技術，能在一個時脈週期就能完成符號偵測。本數據機的特點在於架構簡單，不需昂貴的數位／類比轉換器，僅以正反器採正、負雙緣偵測的策略就可以達到雙倍訊號取樣之效果。而頻率鍵移訊號之偵測則以簡單的轉態計數技術來完成，大幅降低封包偵測與時序還原電路的複雜度。本數據機的設計符合美國FCC對窄頻電力通訊的頻寬規範，能夠在400k Hz的頻寬內達到100k bps傳輸速率。模擬顯示在白高斯雜訊(AWGN)下，採用M路雙正交鍵移直接序列展頻加上頻率鍵移技術可提供額外的2.4 dB的訊雜比增益，而系統的誤碼率在訊雜比達到9.5dB時即可降到10^(-4)。整個數據機的基頻電路並以FPGA加以實現，只需要不到3,000個邏輯閘的複雜度。

關鍵字

窄頻電力線通訊 ； 傳收機 ； M路雙正交鍵移 ； 直接序列展頻 ； 可程式邏輯閘陣列

並列摘要

Targeting intelligent household control applications, a low complexity baseband transceiver design for power line communication is presented. A power line communication simulation model is developed first, where noise sources unique to the power line, i.e., colored background noise, narrow band noise, and impulse noise are characterized mathematically. Subject to the feedback of simulation results, the proposed baseband transceiver adopts a two-stage modulation approach starting with M-ary Bi-Orthogonal Keying (MBOK) based Direct-Sequence Spread Spectrum (DSSS) modulation followed by an FSK scheme. The MBOK scheme employs length-8 modified Walsh codes to minimize the correlation sidelobes for better symbol detection in the presence of large interferences. The FSK scheme is aimed at combating the effects of severe channel attenuation and additive noises. Combining these two schemes leads to a very robust design suitable for power line communication. Eight-way parallel symbol detection strategy is used so that 1 out of 16 modified Wash codes can be correctly identified in every clock cycle. The proposed design also features low circuit complexity in implementation. No A/D or D/A converters are required and FFs alone serve the purpose. The FSK demodulation is accomplished by using a simple transition counting technique. Occupying a bandwidth of 400 kHz, which is compliant with the US FCC regulation, the proposed design owns a 200 kHz chip rate and is capable of supporting a reliable 100 kbps data rate. Simulation results show that the MBOK scheme achieves an additional 2.4 dB SNR gain on the top of the FSK scheme and the BER of the combined schemes can be lower than 10-4 when the SNR value reaches 9.6 dB at AWGN. The FPGA implementation results also indicate the baseband kernel design consumes less than 3,000 logic gates and features a low circuit complexity and protocol robust solution.

並列關鍵字

narrowband PLC ； transceiver ； MBOK ； DSSS ； FPGA