Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves

Sameh M. Shohdy ； Ashraf B. El-Sisi ； Nabil Ismail

《International Journal of Network Security》 11卷3期 (2010/11) Pp. 155-162

https://doi.org/10.6633/IJNS.201011.11(3).05

並列摘要

The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Galois field multiplier, which is implemented using field programmable gate arrays (FPGAs). The multiplier of Galois field based on Karatsuba's divide and conquer algorithm allows for reasonable speedup of the top-level public key algorithms. Binary Karatsuba multiplier is more efficient if it is truncated at n-bit multiplicand level and use an efficient classic multiplier algorithm. In these work three levels to truncate Binary Karatsuba algorithm (4 bits, 8 bits and 16 bits) are chosen showing that 8 bits is the best level for minimum number of slices and time delay to truncate Binary Karatsuba algorithm which is designed on an Xilinx VirtexE XCV2600 FPGA device. The VHDL hardware models are building using Xilinx ISE foundation software. This work is able to compute GF (2191) multiplication in 45.889 ns. experimental results of comparing block and stream ciphers when used to secure VoIP in terms of end-to-end delay and subjective quality of perceived voice.

並列關鍵字

AES ； CBC ； MOS ； QoS ； VoIP