Using Stack Reconstruction on RTL Orthogonal Scan Chain Design

In this paper, we propose an orthogonal scan chain embedded into the RTL design described by Verilog. We first construct the data path graph from the embedded scan chains and then find all the orthogonal scan paths with the minimum weighted cost. These paths share with original data paths as possible. Finally, we create a stack form to reconstruct all the orthogonal scan paths to manage the I/Os and reduce the length and width of stack form as well as decrease the overheads of area and timing. Experimental results show our RTL orthogonal scan chain approach can save up to 13.8% and 5.1% in area overhead than that of the gate-level scan and functional order RTL scan, respectively.

並列關鍵字

RTL scan ； orthogonal scan chain ； area overhead ； timing overhead ； fault coverage

被引用紀錄

Wu, J. O. (2007). 低延遲、傾斜與串音時脈樹合成策略之研究 [doctoral dissertation, National Taipei University of Technology]. Airiti Library. https://doi.org/10.6841/NTUT.2007.00169

國際替代計量

Using Stack Reconstruction on RTL Orthogonal Scan Chain Design

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