Due to the requirement of integrated circuit density, the technology of three-dimensional integrated circuit (3-D IC) is developed to improve the performance of system and the through silicon via (TSV) for vertical stacked technology is a high efficiency methodology. However, the yield of TSV is still low nowadays. Hence, this paper proposes an on-line error detection and correction techniques for TSV in 3-D IC. The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design improves the yield of TSV up to 99.9% and has good performance in area and TSV overhead.