- 期刊
磊晶成長砷化（鎵）銦通道層於矽基板上對高效率低耗能電晶體之應用
Epitaxial Growth of A (Ga)InAs Channel on Si Substrate for High-performance Low-power- consumption Transistor Application
摘要
本研究將描述關於三五族半導體結合矽基板的磊晶技術對高效率低耗能電晶體的應用，包含In_(0.52)Ga_(0.48)As漸變緩衝層(In_(0.52)Ga_(0.48)As Graded-metamorphic Buffer Layer)、介面錯位差排陣列(Interfacial Misfit Dislocation, IMF)與兩階段磊晶技術成長InAs奈米線於矽基板上。使用In_(0.52)Ga_(0.48)As漸變緩衝層磊晶技術可以有效釋放In_(0.52)Ga_(0.48)As通道層與GaAs/Si模板間因晶格不匹配所產生應力，但整體緩衝層厚度將會大於2um。幸運的是對於平面式InAs薄膜磊晶成長於GaAs/Si上而言，界面錯配缺陷法可有效用來降低整個緩衝層厚度並使上層InAs通道層保持極佳的磊晶品質。本文也介紹一些三五族通道材料成長於Si基板上的元件特性。因奈米線本身具有極佳閘極控制能力及在磊晶過程中幾乎沒有缺陷產生等優點，使一維InAs奈米線成長於Si基板上亦受到極大矚目。兩階段成長法能幫助降低InAs奈米線直徑(平均為28nm)及提升奈米線密度(~80/um^2)。垂直式InAs穿隧式場效電晶體於Si基板上元件特性於本文中亦有相關介紹。
並列摘要
The research describes some of the epitaxial techniques of III-V semiconductor growth on Si for high-performance low-power-consumption transistor applications, including In_(0.52)Ga_(0.48)As graded metamorphic buffer, interfacial misfit dislocation (IMF), and two-step-growth InAs nanowire on Si. High stress relaxation of 99% for In_(0.52)Ga_(0.48)As channel growth on GaAs/Si template can be achieved by using graded metamorphic buffer technique. But thick buffer thickness (＞2um) is necessary for getting high-quality In_(0.52)Ga_(0.48)As channel on Si substrate. Fortunately, using IMF technique for planar InAs growth on GaAs/Si template can effectively reduce the entire buffer thickness and keep the upper InAs channel quality high. This article also shows the device performance of III-V channel material grown on Si substrate. 1D InAs nanowire on Si has also attracted much attention because of the good gate controllability and no dislocation formation during material growth. Two-step-growth technique can assist in reducing InAs nanowire diameter (Ave.~28nm) and enhancing the InAs nanowire density to 80/um^2. The device performance of vertical InAs tunneling FET on Si will also be introduced in this article.