Self-adjusting Mechanism for Reducing the Impact of PVT Variations on Clock Skew

Tsung-Tang Lin ； Wen-Pin Tu ； Shih-Hsu Huang

《電機工程學刊》 21卷6期 (2014/12) Pp. 225-233

https://doi.org/10.6329/CIEE.2014.06.03

並列摘要

As the process technology continues to shrink, the effect of process/voltage/temperature (PVT) variations on clock skew has become a serious concern. During the post-silicon stage, it is known that adjustable delay buffers (ADBs) can be utilized to balance the clock skew. However, in fact, unless ADBs have a self-adjusting mechanism, the clock skew caused by PVT variations cannot be suppressed. In this paper, we propose a self-adjusting mechanism that can dynamically configures the delays of ADBs for suppressing the effect of PVT variations on clock skew. The proposed self-adjusting mechanism is composed of the following four stages: capture, comparison, measurement, and quantification. Experiments with benchmark circuits consistently show that the proposed self-adjusting mechanism can effectively suppress the clock skew caused by PVT variations.

並列關鍵字

Adjustable Delay Buffer ； Clock Distribution Network ； Clock Skew ； Dynamic Adjustment ； PVT Variations