Two-Port SRAM Cell with Improved Write Operation

具有改進寫入操作的雙埠SRAM晶胞

余建政(Chien-Cheng Yu) ； 蕭明椿(Ming-Chuen Shiau)

《修平學報》 38期 (2019/03) Pp. 1-14

摘要

In this paper, a novel seven-transistor (7T) two-port SRAM cell incorporating an assist circuit is proposed. Wherein, the assist circuit is used to deal with the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located near to the write bit line. Accordingly, it can provide an efficient solution to the writing '1' issue to improve write operations in this manner. Simulation results for the proposed cell design confirm that there is a conspicuous improvement over the conventional two-port SRAM cells, and fast writing also can be achieved.

關鍵字

Two-port ； Assist circuit ； Single-ended ； Static random access memory ； Read- write control circuit

並列摘要

眾所周知，在配置有單端位元線的靜態隨機存取記憶體（SRAM）晶胞中，無論何時執行寫入操作，都可能發生寫入失敗。尤其是，如果記憶晶胞目前儲存邏輯“0”，則對晶胞寫入邏輯“1”是相對困難的。因此有必要提供一種解決記憶晶胞中的寫入失敗的方法。本論文提出一種結合輔助電路的新型雙埠SRAM晶胞。其中，輔助電路用於處理記憶晶胞的寫入失敗。在寫入操作期間，該輔助電路被啟動以將呈二極體連接的電晶體連接到位於寫入位元線附近的驅動電晶體的源極，如此可以提供一種解決寫入‘1’問題的有效方案來改進寫入操作。本論文所提出的晶胞設計經過模擬結果證實，與傳統的雙埠SRAM晶胞相比具有顯著的改進，並且還可以實現快速寫入。

並列關鍵字

雙埠 ； 寫入操作 ； 靜態隨機存取記憶體 ； 讀寫控制電路

參考文獻

J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Designer Perspective, 2nd ed., Upper Saddle River, NJ: Prentice-Hall, 2003.

K. Itoh, VLSI Memory Chip Designs, Heidelberg, Springer-Verlag, 2001.

H. Tran, “Demonstration of 5T SRAM and 6T Dual-Port RAM Cell Arrays,” in Proc. 1996 Symp. VLSI Circuits Dig. Tech. Papers, 1996, pp. 68-69.

Y. Luthra, ”Dual port SRAM with dedicated read and write ports for high speed read operation and low leakage,” U.S. Pat. 7813161, Oct. 12, 2010.

K. Nii, et al., "Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM with Circumvention of Simultaneous Common-Row-Access," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 977-986, Mar. 2009.