- 期刊
Dynamic Relocation Cache for Instruction Delivery in Low Power Processor
摘要
A set-associative cache wastes power because the parallel access to multi-bank memory consumes a lot of power. In this paper, we present a cache architecture (Dynamic Relocation (DR) Cache) that serves as a low-power instruction source instead of the set-associative cache. Not restricted to the static layout imposed by compiler, DR cache is capable of storing instructions in an execution sequence by using a hardware-only method without software or compiler. The trace-based storing scheme, which is capable of storing instructions in an execution sequence, makes sure that DR cache could provide a high hit rate with a small single-bank data memory. We evaluate DR cache in runtime performance and power, and then compare it with the following caches: direct-mapped, 2-way set-associative and 4-way set-associative cache. The comparison is accomplished by running ten embedded programs on a RTL (Register Transfer Level) hardware model based on the LEON3 processor. The evaluation shows that, on average, the 4-kB DR cache provides the same performance in hit rate and an 83% reduction in power consumption compared to the 4-kB 4-way set-associative cache. The 4- kB DR cache also surpasses other caches in what we define as follows: (1) the power with comparable area, and (2) the smallest power.