Optimized Nanometric Fault Tolerant Reversible BCD Adder

Majid Haghparast ； Masoumeh Shams

《Research Journal of Applied Sciences, Engineering and Technology》 4卷9期 (2012/05) Pp. 1067-1072

並列摘要

In this study a novel nanometric fault tolerant quantum and reversible binary coded decimal adder is proposed. Reversible logic has found emerging attentions in optical information processing, quantum computing, nanotechnology and low power design. BCD Adder is a combinational circuit that can be used for the addition of two numbers in BCD arithmetic's. The proposed reversible BCD adder has also parity preserving property. It is better than all the existing counterparts. The proposed circuit is optimized. It is compared with the existing circuits in terms of number of constant inputs, number of garbage outputs, quantum cost and hardware complexity. All of the parameters are improved dramatically. It is to be noted that all the circuits have nanometric scales.

並列關鍵字

Binary coded decimal adder ； fault tolerant ； nanotechnology based systems ； nanometric circuits ； quantum computing ； quantum circuits ； quantum gates ； reversible logic