An Effective Bidirectional Network on Chip with Pipelining and Self Reconfigurable Channel

A. Rajalingam ； Bechtel Brabi

《Research Journal of Applied Sciences, Engineering and Technology》 7卷22期 (2014/06) Pp. 4714-4719

並列摘要

The Bidirectional Network on Chip (Bi-NoC) architecture is more efficient than the conventional architecture because in conventional architecture the unidirectional flow is used where as in Bi-NoC the two way data flow can be performed. The XY routing algorithm is used to perform the architecture. The Bi-NoC architecture allows each channel to transmit in all direction and increases the bandwidth, reduces the access latency and reduces power consumption. The pipelining architecture is used in this study instead of parallel architecture because this performs the reduction in size of the architecture with better result. Also it produces better transmission in the router with reduced traffic and also has less amount of access latency which enhances the performance through better resource utilization. In this proposed method the number of flip flops reduced by 35.9% and the access latency is reduced by 18.9% when compared to existing method.

並列關鍵字

Channel allocator ； masked and unmasked arbiter ； pipelining ； virtual channel