Design and Implementation of Low Power AES SBOX with Error Detection Circuit

V. Devendiran ； S. Letitia

《Research Journal of Applied Sciences, Engineering and Technology》 10卷7期 (2015/07) Pp. 824-830

並列摘要

Soft error is nowadays a serious problem when implementing AES SBOX algorithms in hardware. The objective of the study is to detect the error using parity bit for the AES SBOX and implementation in hardware with low area and power. This circuit can products the AES Encryption/Decryption process and systems against fault based attacks. It can also apply to any digital communication systems and security related applications.

並列關鍵字

AES SBOX ； error detection ； low area