VLSI Architecture Using a Modified SQRT Carry Select Adder in Image Compression

K. Indiradevi ； Dr. R. Shanmugalakshmi

《Research Journal of Applied Sciences, Engineering and Technology》 11卷1期 (2015/09) Pp. 14-18

並列摘要

Designing a compressor with the parameters such as power, delay and area are most considerable metric in VLSI design. Compression process plays a vital role in image processing and the main building block is the multiplier. Image conversion is done in MATLAB and the compression is done using VHDL in VLSI. Finally, the compression ratio is predicted using MATLAB. CPA (Carry Propagation Adder) and CSA (Carry Save Adder) occupies more chip area than other adders. To overwhelm the problem this study proposes a modified Square Root Carry Select Adder (SQRT CSLA) in Dadda multiplier used in compression system. The modified SQRT CSLA performs faster than other adders and power consumption is low. Compression techniques pay more attention in image processing. In this study 4-2 compressor is employed to reduce the complexity.

並列關鍵字

Dadda multiplier ； image compression ； modified Square Root Carry Select Adder (SQRT CSLA)