Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

KISEON CHO ； MINKYU SONG

《VLSI Design》 2002卷 (2002/12) Pp. 249-258

https://doi.org/10.1080/10655140290011050

摘要

In general, an arithmetic logic unit (ALU) of a DSP core is composed of an adder, multiplier and shifter. In order to obtain a high-performance 32-bit ALU, in this paper, an adaptive leaf-cell based layout technique is proposed. Thus novel architectures of 64-bit adder, 32 x 32-bit multiplier, and 32-bit shifter are proposed. The architecture of the proposed 64-bit adder is based on the conditional select addition with regular adaptive multiplexers. Secondly, novel optimized data compressors with a compound logic are proposed in a 32 x 32-bit multiplier. Finally, a shift algorithm with a pre-mask decoder is proposed for the 32-bit barrel shifter. They have been fabricated with 0.25 mm 1-poly 5-metal CMOS process, and we have obtained desired experimental results.

關鍵字

Arithmetic logic unit ； Leaf-cell based layout ； Conditional select adder ； Multiplier with data compressor ； Barrel shifter with a pre-mask decoder