- 期刊
Design of Asynchronous FIFO Controller Based on FPGA
摘要
In order to improve the real-time and high-efficiency of data transmission in the label printer, an asynchronous FIFO controller based on FPGA (Field Programmable Gate Array) was designed, and the Verilog HDL hardware description language was used to realize the asynchronous FIFO data read and write control. A practical method to solve the problem of metastable state and competition risk in asynchronous FIFO. Through simulation experiment test, it is shown that the design of the controller is stable and reliable, the data can be input and read stably, and the utilization rate of system resources is improved, To ensure the high-speed data transmission requirements of the label printer.
參考文獻
N. Bu, R. Zhang, Z. J. Liu. Research status and development strategies of inkjet printing technology, Packaging Engineering, (2018) No.17, p. 236-242.
D. Lu, J. H. Zhang, et al. Design and implementation of a multi-channel FIFO memory controller based on FPGA, Modern Electronic Technology, (2019) No.42, p. 1-4.
Y. Y. Xu. Multi-channel large-capacity FIFO design based on FPGA, Electronic Measurement Technology, (2017) No.40, p. 193-197.
Y. P. Zhang, S. J. Ye. Improved design of virtual FIFO based on FPGA, Journal of Shenyang University of Technology, (2016) No.31, p. 298-303.
Z. W. Zhang, H. Jin, S. B. Yang. USB3.0 high-speed reading interface design of high-speed and large-capacity recorder, Application of Electronic Technology, (2016) No.42, p. 54-57.