應用於2.4GHz ISM頻帶之三角積分調變除小數頻率合成器

A 2.4GHz ISM Band Frequency Synthesizer with a Delta-Sigma Modulator

李國豪(Guo-Hau Lee)

指導教授 ： 呂良鴻

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.00005

摘要

在無線通訊系統中，為了在有限的頻寬內容納更多的用戶，窄通道間距以及在頻帶間的快速切換是必須滿足的條件。除小數鎖相迴路(fractional-N phase-locked loop)的架構被廣泛的應用來達成這些需求。為了要減輕雜訊及分數突波(fractional spurs)所造成的問題，我們採用了三角積分調變器(delta-sigma modulator)來減小在頻率合成器頻寬內之雜訊。如此可改善分數突波以及雜訊表現。
本論文實現了一個包含單晶壓控震盪器的2.4 GHz ISM頻帶三角積分調變除小數頻率合成器。藉由運用E-TSPC形式的預除器，除法器電路可以同時實現高速除頻及低功率消耗的特點。此除法器並不需要額外消耗大量功率的預放大器(preamplifier)或緩衝級來驅動。整體晶片包含相位頻率偵測器(PFD)，電荷幫浦(CP)，壓控震盪器(VCO)以及多除數除法器(MMD)。低通濾波器的部份由外接元件所實現。三角積分調變器的輸出由向量產生器(pattern generator)所提供。晶片以台積電0.35-μm 2P4M CMOS 製程所製作，頻率合成器的功率消耗為 27 毫瓦。量測於鎖定時的相位雜訊為 -97 dBc/Hz @ 1MHz 偏移。晶片的面積為894 × 855 μm2。

關鍵字

除小數 ； 三角積分調變 ； 頻率合成器

並列摘要

In a wireless communication system, narrow channel spacing and fast switching time between channels are desirable to accommodate more users due to the limited frequency band. A fractional-N phase-locked-loop (PLL) architecture is a widely used technique to meet the demands. In order to alleviate the problems caused by fractional spurs and noises, the delta-sigma modulator (DSM) technique is adopted to reduce the phase noise within the synthesizer bandwidth. As a result, the fractional spurs and noises performance can be improved.
A 2.4 GHz ISM-band fractional-N frequency synthesizer with a monolithic voltage-controlled oscillator is presented in this thesis. By utilizing the E-TSPC type prescaler, the divider circuit can achieve both high-speed frequency division and low power consumption. No power hunger preamplifier or buffer is needed to drive the divider. The chip is composed of a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO) and a multi-modulus divider (MMD). The required low-pass filter is provided by off-chip components in this design. The DSM output is provided by pattern generator. Fabricated in a TSMC 0.35-μm 2P4M CMOS technology, the power consumption of the synthesizer is 27mW. The measured phase noise performance in lock state is -97dBc/Hz @ 1MHz offset. The chip area is 894 × 855 μm2.

並列關鍵字

E-TSPC ； frequency synthesizer ； fractional-N ； Delta-Sigma

參考文獻

[1] Emad Hegazi, and Asad A. Abidi, “A 17-mW Transmitter and Frequency Synthesizer for 900-MHz GSM Fully Integrated in 0.35-m CMOS,” IEEE J. Solid-State Circuits,” vol. 38, pp. 782-792, May 2003.

[2] Bram De Muer, and M. S. J. Steyaert, “A CMOS Monolithic SD-Controlled Fractional-N Frequency Synthesizer for DCS-1800,” IEEE J. Solid-State Circuits, vol. 37, pp. 835-844, July 2002.

[3] Michael H. Perrott, “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2059, Dec. 1997.

[4] Michael H. Perrott, “A Modeling Approach for S–D Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002.

[5] S. Cicero, and Zhenhua Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 1039-1045， July 2000.