結合高度數位化延遲迴路補償及動態元件匹配技術之30/50-MHz頻寬連續時間三角積分調變器

A 30/50-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Incorporating Highly-Digital ELD Compensation with DEM Technique

金邦諺(Pang-Yen Chin)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603721

摘要

對於能夠支援高達幾千萬赫茲訊號頻寬的連續時間三角積分調變器來說，由於調變器通常操作在幾十億赫茲的取樣頻率之下，最小化迴授路徑中電路的延遲變得更具挑戰性。然而在迴授路徑中除非架構有所改進，動態元件匹配是經常被運用以提高線性度之技術，其所造成的延遲是無法避免的。
此論文呈獻一個四階三位元連續時間三角積分調變器，提出結合高度數位化延遲迴路補償及動態元件匹配之技術，以降低電路在迴授路徑上受到的時間限制，並且減少電路的功耗與面積。此技術經模擬驗證，具有一定的功能，足以使迴路穩定且達到高度訊號雜訊比。
本晶片使用台積電四十奈米互補式金屬氧化物半導體1P10M 製程所實現，經測試分別操作於十六億赫茲和二十億赫茲的取樣頻率，在三千萬赫茲和五千萬赫茲的訊號頻寬下，最高可達64.8dB 及56.5dB 的訊號雜訊失真比。晶片在1.2 伏特與1.5 伏特的電源供應下總共消耗23.65 毫瓦，核心面積僅0.141 平方毫米。

關鍵字

連續時間三角積分調變器 ； 迴路延遲補償 ； 動態元件匹配

並列摘要

For a continuous-time delta-sigma modulator (CTDSM) supporting signal bandwidth up to tens of megahertz, minimizing delay in feedback paths has become more challenging, as the modulator usually operates at multi-gigahertz clock rate. However, for the required linearity, dynamic element matching (DEM) technique has always been used, the delay is inevitable unless there’s an improvement in architecture.
This thesis presents a fourth-order three-bit continuous-time delta-sigma modulator that incorporates highly-digital excess loop delay compensation with dynamic element matching technique, the combination helps relax timing constraint on circuits in feedback paths and reduce power consumption and chip area. Loop stability and noise performance have been observed with functionality by simulation.
Fabricated in TSMC 40nm GP 1P10M technology, the proposed CTDSM is tested to operate at 1.6GHz and 2GHz, achieving peak SNDR of 64.8dB and 56.5dB over a 30MHz and 50MHz signal bandwidth, respectively. The chip dissipates 23.65mW from 1.2V/1.5V supplies. And the active area of this modulator occupies only 0.141〖mm〗^2.

並列關鍵字

Continuous-time delta-sigma modulator ； DEM ； excess loop delay compensation

參考文獻

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