- 學位論文
具相位誤差校正之延遲鎖定迴路設計與實現
Design and Implementation of Delay-Locked Loops with Static Phase Error Calibration
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摘要
在傳統CMOS充電泵電路會有一些造成電流不匹配的問題，然而這些電流不匹配的問題產生將造成延遲鎖定迴路或鎖相迴路的輸出發生相位偏移的現象以致降低整體系統的性能。在本篇論文裡描述延遲鎖定迴路系統架構設計及應用和以使用了三種不同的系統架構來改善輸出相位誤差的問題，且在這系統中並不需要額外多複製一組充電泵，即可達到改善同步系統中相位誤差的問題；並且使用了0.18微米CMOS 製程來製作出整體系統架構，以驗證我們所提出電路技巧以及量測其校正前與校正後的改善效果。 首先，使用自動追蹤能力的數位充電泵電流校正的技巧應用在延遲鎖定迴路系統中來改善充電泵充放電流不匹配的問題；並分別使用一時間放大電路[9]將不同輸入的兩個相位作時間差放大的技巧和另提出一個適合應用在延遲鎖定迴路系統上，新式的可變延遲時間的相位頻率偵測器來放大原迴路的相位錯誤，來增加相位誤差的偵測解析度以作充電泵充放電流的更細部單位的調整。 接著，我們提出一種數位分離式重置時間的相位頻率偵測器的電路技巧，將相位頻率偵測器輸出控制充電泵充放電流的UP與Down的訊號作不同時間的延遲重置，來直接對錯誤的相位做位移的動作，以達到相位對齊的目的。 在我們設計三個電路系統中皆以能涵蓋10%的製程變異，且皆能達到相位誤差校正的效果。三個電路系統整體面積，分別皆為0.85mm * 1.0mm ，在參考頻率500MHz、電源供應電壓為1.8伏特時，整體電能消耗也都小於30mW。
並列摘要
Conventional CMOS charge-pump circuits have some current mismatch problems. The current mismatch induces a phase error which deteriorates the performance of delay-locked loop systems or phase-lock loop systems. In this dissertation, we describes on the design and application of delay-locked loop systems and we use three architectures and circuits to improve the phase error in the synchronization systems, and there is no extra replica charge-pump needed; these architectures and circuits have been fabricated in 0.18µm CMOS to verify the circuits technique and measure the systems calibration result. Hence, using a digital technique with auto-tracking ability to calibrate the current mismatch of the charge-pump in delay-locked loop systems; and one chip is using a time amplifier[9] to amplify two different input phase and in the other chip, we propose a new switched-delay phase-frequency detector is well suited to the delay-locked loop systems to magnify the phase error in the original system, that increase the phase detectable resolution of phase-frequency detector to fine tune charge-pump calibration. Next, we propose a new technique is digital different reset time of phase-frequency detector circuit to separate UP and Down that are outputs of phase-frequency detector that control charge-pump will charge or discharge reset time, that will shift the location of phase error to achieve in-phase. We design three architectures and circuits can cover 10% process variation, and these are all can improve the phase error. The area of these three chips were all 0.85mm * 1.0mm, and reference frequency is 500MHz and voltage on power supply is 1.8V, the power consumes was less than 30mW.
參考文獻
[1] C. F. Liang, S. H. Chen, and S. I. Liu, “A digital calibration technique for charge pumps in phase-locked systems”, IEEE J. Solid-State Circuits, vol. 43, pp. 390-398, Feb. 2008.
[2] Y. Moon, D. K. Jeong, and G. Ahn, “A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery “, IEEE J. Solid-State Circuits, vol. 36, Dec. 2001.
[3] T. H. Lee, K. Donneily, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa, “A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM”, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 300-301, Feb. 1994.
[4] B. G. Kim, L. S. Kim, “A 250MHz-2GHz wide range delay-locked loop“, IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, June 2005.
[5] R. M. Weng, T. H. Su, and C. Y. Liu, “A CMOS 2.4 GHz delay-locked loop based programmable frequency multiplier”, Consumer Electronics, pp. 371-372, Jan. 2006.