- 學位論文
基於IEEE 1500標準HBM PHY互連測試
IEEE 1500 Based HBM PHY Interconnect Testing
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摘要
本文探討了HBM PHY互連的測試問題。HBM是一種使用TSV連接堆疊記憶體晶片的高頻寬低功耗的DRAM，適用於圖形處理器、高性能計算、人工智慧和機器學習等領域。HBM和SoC之間透過矽中介板連接數位I/O訊號，互連可能發生故障，影響系統性能和可靠性。傳統的探針測試方法不適用於HBM PHY互連，因此需要有效的測試方案。本文提出了一個基於內建自我測試（BIST）的測試方案，整合了現有的串擾故障測試方案，並設計了一個最佳化的短路故障測試圖樣。本文還考慮了後續診斷和通道修復的功能，對HBM PHY互連的功能進行驗證，提高HBM PHY互連的測試覆蓋率和可靠性。
並列摘要
This paper investigates the testing problem of HBM PHY interconnects. HBM is a high-bandwidth low-power DRAM that uses TSVs to connect stacked memory chips, suitable for graphics processors, high-performance computing, artificial intelligence and machine learning applications. HBM and SoC are connected by silicon interposer for all digital I/O signals, and interconnect faults may occur, affecting system performance and reliability. Conventional probe testing methods are not applicable to HBM PHY interconnects, so an effective testing scheme is needed. This paper proposes a BIST-based testing scheme that integrates the existing crosstalk fault testing scheme and designs an optimized short-circuit fault test pattern. This paper also considers the subsequent diagnosis and lane repair functions, and verifies the functionality of HBM PHY interconnects. The contribution of this paper is to improve the test coverage and reliability of HBM PHY interconnects, and reduce the test cost and time.
參考文獻
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