透過您的圖書館登入
IP:18.216.219.130
  • 學位論文

具低靜態電流與快速暫態響應之被動式斜坡延長導通時間控制降壓型轉換器

A Passive Ramp Extended-On-Time Controlled Buck Converter with Low Quiescent Current and Fast Transient Response

指導教授 : 陳景然
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


隨著行動裝置的普及,針對系統晶片的高效能電源管理積體電路需求日益增長。雖然以往研究已針對寬負載範圍內保持高效率、實現快速負載暫態響應及快速動態電壓調節等問題分別提出了解決方案,但至今尚無研究能夠同時解決這些問題。   本論文提出了被動式斜坡延長導通時間控制的降壓型轉換器,其適用於行動裝置,並同時具備三項特點:在寬負載範圍皆能維持高效率、具備快速暫態響應和動態電壓調節。另外,透過小信號分析得到頻寬內零極點的特性,也就是使用誤差放大器和單一原點補償電容便能夠進行調節,從而使得誤差放大器的靜態電流可隨其補償電容同時往下調整,以增加輕載效率。   除此之外,本論文提出了鉗位機制解決了誤差放大器輸出電壓飽和的問題,並搭配延長導通時間使抽載的輸出欠壓減少了四倍。此外,本論文提出了一動態偏置的誤差放大器,以加速動態電壓調節,使動態電壓調節響應速度比使用傳統誤差放大器快三倍。並因為控制的特性,實現了從連續導通模式到不連續導通模式的無縫過渡。   本論文之晶片採用TSMC 0.18 µm CMOS製程,在連續導通模式下切頻為4 MHz,靜態電流僅2 µA,在40 µA到1.2 A的30000倍負載電流範圍內均達到大於85%的效率。另外,在暫態響應中,當負載為1 A / 100 ns的電流步階時,其恢復時間為1.96 µs,並且輸出欠壓為80 mV。至於動態電壓調節的表現,輸出電壓從1.25 V上升到1.8 V的穩定時間為2.8 µs,而在連續導通模式與不連續導通模式切換之間,輸出電壓的擾動小於24 mV。

並列摘要


With the widespread use of mobile devices, the demand for high-performance power management integrated circuits (PMICs) for system-on-chips (SoCs) is increasing. While prior research has individually tackled challenges such as maintaining high efficiency across a wide load range, achieving fast load transient response, and enabling quick dynamic voltage scaling (DVS), a comprehensive solution addressing all these issues simultaneously has not been achieved in previous studies。  This thesis proposes a passive ramp extended-on-time (PR-ETON) controlled buck converter suitable for mobile devices, featuring three main characteristics simultaneously: high efficiency over a wide load range, fast transient response, and fast DVS. Through small signal analysis, zero pole in-band characteristic is obtained, allowing the use of type-I compensation, which involves only an integrator error amplifier (EA) and a single compensation capacitor, allowing the quiescent current of EA to be scalable with its compensation capacitor to enhance light load efficiency.  Additionally, a clamping mechanism is proposed to address the issue of the EA's output voltage saturation. When combined with the extended-on-time control, this mechanism reduces load transient output undershoot by four times. Furthermore, an adaptive biased EA is proposed to accelerate DVS response, making the DVS response three times faster than using conventional error amplifiers. The control characteristics also enable seamless transition between continuous conduction mode (CCM) and discontinuous conduction mode (DCM).  The chip, fabricated using TSMC's 0.18 µm CMOS process, operates at a switching frequency of 4 MHz in CCM and has a quiescent current of only 2 µA. It achieves greater than 85% efficiency across a 30,000 times load current range from 40 µA to 1.2 A. In the load transient response, the recovery time is 1.96 µs with a 1 A / 100 ns load current step, and the output voltage undershoot is 80 mV. For DVS performance, the output voltage stabilizes in 2.8 µs when rising from 1.25 V to 1.8 V. Moreover, during the transition between CCM and DCM, the output voltage perturbation is less than 24 mV.

參考文獻


[1] M. S. Ahmed and A. A. Fayed, "A Current-Mode Delay-Based Hysteretic Buck Regulator With Enhanced Efficiency at Ultra-Light Loads for Low-Power Microcontrollers," IEEE Trans. Power Electron, vol. 35, no. 1, pp. 471-483, Jan. 2020.
[2] A. Besharati Rad, M. Kargaran, M. Meghdadi and A. Medi, "A Wide-Input-/Output-Voltage-Range Buck Converter With Adaptive Light-Load Efficiency Improvement and Seamless Mode Transition," IEEE Trans. Power Electron., vol. 39, no. 2, pp. 2200-2212, Feb. 2024.
[3] W. Hong and M. Lee, "A 7.4-MHz Tri-Mode DC-DC Buck Converter With Load Current Prediction Scheme and Seamless Mode Transition for IoT Applications," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 67, no. 12, pp. 4544-4555, Dec. 2020.
[4] J. Kang, J. Park, M. Jeong and C. Yoo, "A Time-domain-controlled Current-mode Buck Converter With Wide Output Voltage Range," IEEE J. Solid-State Circuits, vol. 54, no. 3, pp. 865-873, March 2019.
[5] D. -H. Jung, K. Kim, S. Joo and S. -O. Jung, "0.293-mm2 Fast Transient Response Hysteretic Quasi- V2 DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- μ m CMOS," IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1844-1855, June 2018.

延伸閱讀