- 學位論文
遠端串音干擾消除與前饋式等化器共同設計之8Gbps傳輸機輸出級電路/ 數位振盪器之電路佈局產生器
An 8 Gbps Far-End Crosstalk Cancellation and FFE Co-designed TX Output Driver / Digitally-Controlled Oscillator Layout Generator
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摘要
本論文介紹了一種單端傳輸機輸出級電路，該驅動器結合了前饋式等化器（feed-forward equalizer）和遠端串音干擾（far-end crosstalk）消除技術，所提出的傳輸機輸出級電路對靜態模式與偶模式信號應用不同強度的前饋式等化器，從而消除了兩條並聯微帶線之間串音所引起的串音干擾引起抖動（crosstalk induced jitter），同時保存奇模式信號固有的高頻補償特性以進一步補償通道損耗。在28 奈米CMOS 製程下，所實現之傳輸機晶片於8Gbps 的傳輸速度下可使峰對峰抖動（peak-to-peak jitter）和串音干擾引起抖動分別減少48 個（29 ps）和114 個百分比，並擴張眼圈之水平張開幅度（位容錯率小於1e12）34 個百分比。 在有線傳輸的應用中，鎖相迴路提供的時脈訊號品質將直接影響傳輸機的性能表現，而鎖相迴路中的振盪器往往需要大量的設計迭代來實現最佳效能。本論文同時介紹了一種數位控制振盪器之電路佈局產生器（digitally-controlled oscillator layout generator），來大幅降低電路佈局所需耗費的時間。藉由所開發之佈局產生器，設計者可以根據所設計的環狀振盪器之電晶體尺寸與級數及數位類比轉換器（digital-to-analog converter）之位元數，直接輸入設計參數於數位控制振盪器佈局產生器，來自動生成數位控制振盪器的電路佈局。因此，我們可以大大節省設計電路後所耗費在電路佈局上的時間，減少執行後模擬(post-simulation)流程所需要的時間成本，進而加速研發時間。
並列摘要
This thesis present a single-ended TX output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver eliminates the crosstalk induced jitter (CIJ) between two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for channel loss compensation. Implemented in a 28nm CMOS technology, the driver reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER <1E12) by 34%. In wireline communication design, the quality of the clock signal from a phase-locked loop (PLL) directly impacts system performance. Nevertheless, the oscillators within the PLL often necessitate extensive design iterations to attain optimal performance. This thesis also introduces a layout generator for a digitally-controlled oscillator (DCO). With the DCO layout generator, designers can specify the MOS sizes, stages of the ring oscillator, and the number of bits of the digital-to-analog converter (DAC), and input these design parameters directly into the layout generator. This process automates the generation of circuit layouts for DCOs, resulting in substantial time savings in circuit layout design. Consequently, it diminishes the time cost associated with post-simulation and accelerates development time.
參考文獻
[1] H.K. Jung, K. Lee, J.S. Kim, J.J. Lee, J.Y. Sim, and H.J. Park, “A 4 gb/s 3bit parallel transmitter with the crosstalkinduced jitter compensation using tx data timing control,” IEEE Journal of SolidState Circuits, vol. 44, no. 11, pp. 2891–2900, 2009.
[2] H.K. Jung, S.M. Lee, J.Y. Sim, and H.J. Park, “A slewrate controlled transmitter to compensate for the crosstalkinduced jitter of coupled microstrip lines,” in IEEE Custom Integrated Circuits Conference 2010, pp. 1–4, Sep. 2010.
[3] S.Y. Kao and S.I. Liu, “A 7.5gb/ s onetapffe transmitter with adaptive farend crosstalk cancellation using duty cycle detection,” IEEE Journal of SolidState Circuits, vol. 48, pp. 391–404, Feb 2013.
[4] B. Razavi, Design of Integrated Circuits for Optical Communications. Wiley Press, second ed., 2012.
[5] J. Lee, Communication Integrated Circuits.