- 學位論文
應用於數位電路設計之有效電晶體尺寸優化策略
Efficient Transistor Sizing Optimization Strategy for Digital Integrated Circuit Design
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摘要
在現代數位積體電路設計中，標準元件庫是關鍵基礎。預先設計並最佳化的標準元件有助於大規模電路的合成、佈局、繞線和驗證。然而，標準元件電路的設計和最佳化本身在先進的製程技術中是複雜的。增加的漏電流、複雜的設計規則和受限的佈局空間使得設計滿足電氣特性要求和佈局約束的標準元件成為一項重大挑戰。電晶體尺寸可幫助我們在指定設計約束和所需電路最佳化目標下確定一組電路的最佳電晶體尺寸。基於方程式的方法和基於模擬的方法是過去研究過的兩種電晶體尺寸調整方法。在這項工作中，研究發現基於方程式的方法中使用的近似方程式會導致顯著的電氣特性偏差。基於模擬的方法的最佳化結果可能會受到初始值的嚴重限制。作為對現有方法的改進，提出了一種新的方法來尋找合適的初始值並減少電特性偏差。初步結果表明，所提出的方法在 20 奈米電路最佳化中是有效的。
並列摘要
In modern digital integrated circuit designs, standard-cell libraries are key foundations. The predesigned and optimized standard cells facilitate large-scale circuit synthesis, placement, routing, and verification. However, the standard-cell circuit design and optimization are nontrivial in advanced process technologies. The increased leakage current, complicated design rules, and restrictive layout space make the task of designing standard cells meeting both electrical characteristic requirements and layout constraints a significant challenge. Transistor sizing can help determine an optimal set of transistor sizes of the circuit under specified design constraints and desired circuit optimization goals. Equation-based approaches and simulation-based approaches are two types of transistor sizing methods that have been previously studied. In this work, studies find that the approximate equations used in the equation-based approaches can cause significant electric characteristic deviation. The optimization results of the simulation-based approaches may be severely restricted by initial values. As a refinement of the existing approaches, a new method is proposed to find suitable initial values and reduce the electric characteristic deviation. Preliminary results indicate that the proposed method can be effective in 20-nm-grade circuit optimization.
參考文獻
Neil H. E. Weste, David Harris, CMOS VLSI Design: A circuits and System Perspective, 4th edition, Pearson, 2011.
Wang, Alice, Benton H. Calhoun, and Anantha P. Chandrakasan. Sub-threshold design for ultra low-power systems. Vol. 95. New York: Springer, 2006.
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ, USA: Prentice-Hall, 2003.
Golshan, Khosrow, Physical Design Essentials: An Asic Design Implementation Perspective, Springer, 2007.
Boyd, Stephen, Stephen P. Boyd, and Lieven Vandenberghe. Convex optimization. Cambridge university press, 2004.